| Line 62... |
Line 62... |
constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
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constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
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|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060100"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060202"; -- no touchy!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
-- External Interface Types ---------------------------------------------------------------
|
-- External Interface Types ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
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| Line 947... |
Line 947... |
XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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XIRQ_TRIGGER_POLARITY : std_ulogic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
|
IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
|
|
IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
|
IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
|
|
IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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| Line 1198... |
Line 1202... |
-- data input --
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-- data input --
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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mem_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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alu_i : in std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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-- data output --
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-- data output --
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs1_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
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rs2_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand 2
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cmp_o : out std_ulogic_vector(1 downto 0) -- comparator status
|
|
);
|
);
|
end component;
|
end component;
|
|
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- Component: CPU ALU ---------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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| Line 1227... |
Line 1230... |
rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs1_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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rs2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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pc2_i : in std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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imm_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediate
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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csr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
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cmp_i : in std_ulogic_vector(1 downto 0); -- comparator status
|
|
-- data output --
|
-- data output --
|
|
cmp_o : out std_ulogic_vector(1 downto 0); -- comparator status
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
|
res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
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add_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
|
fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
|
fpu_flags_o : out std_ulogic_vector(4 downto 0); -- FPU exception flags
|
-- status --
|
-- status --
|
idone_o : out std_ulogic -- iterative processing units done?
|
idone_o : out std_ulogic -- iterative processing units done?
|
| Line 1619... |
Line 1622... |
|
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_uart
|
component neorv32_uart
|
generic (
|
generic (
|
UART_PRIMARY : boolean -- true = primary UART (UART0), false = secondary UART (UART1)
|
UART_PRIMARY : boolean; -- true = primary UART (UART0), false = secondary UART (UART1)
|
|
UART_RX_FIFO : natural; -- RX fifo depth, has to be a power of two, min 1
|
|
UART_TX_FIFO : natural -- TX fifo depth, has to be a power of two, min 1
|
);
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
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| Line 1799... |
Line 1804... |
data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
|
clkgen_i : in std_ulogic_vector(07 downto 0); -- "clock" inputs
|
-- CPU state --
|
|
sleep_i : in std_ulogic; -- set if cpu is in sleep mode
|
|
-- interrupt --
|
-- interrupt --
|
irq_o : out std_ulogic; -- interrupt request
|
irq_o : out std_ulogic; -- interrupt request
|
-- custom io (conduit) --
|
-- custom io (conduit) --
|
cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE-1 downto 0); -- custom inputs
|
cfs_in_i : in std_ulogic_vector(CFS_IN_SIZE-1 downto 0); -- custom inputs
|
cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0) -- custom outputs
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cfs_out_o : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0) -- custom outputs
|
| Line 1968... |
Line 1971... |
-- control --
|
-- control --
|
clk_i : in std_ulogic; -- clock, rising edge
|
clk_i : in std_ulogic; -- clock, rising edge
|
rstn_i : in std_ulogic; -- async reset, low-active
|
rstn_i : in std_ulogic; -- async reset, low-active
|
clear_i : in std_ulogic; -- sync reset, high-active
|
clear_i : in std_ulogic; -- sync reset, high-active
|
level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level
|
level_o : out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0); -- fill level
|
|
half_o : out std_ulogic; -- FIFO is at least half full
|
-- write port --
|
-- write port --
|
wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
|
wdata_i : in std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- write data
|
we_i : in std_ulogic; -- write enable
|
we_i : in std_ulogic; -- write enable
|
free_o : out std_ulogic; -- at least one entry is free when set
|
free_o : out std_ulogic; -- at least one entry is free when set
|
-- read port --
|
-- read port --
|
| Line 2130... |
Line 2134... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function or_reduce_f(a : std_ulogic_vector) return std_ulogic is
|
function or_reduce_f(a : std_ulogic_vector) return std_ulogic is
|
variable tmp_v : std_ulogic;
|
variable tmp_v : std_ulogic;
|
begin
|
begin
|
tmp_v := '0';
|
tmp_v := '0';
|
if (a'low < a'high) then -- not null range?
|
for i in a'range loop
|
for i in a'low to a'high loop
|
|
tmp_v := tmp_v or a(i);
|
tmp_v := tmp_v or a(i);
|
end loop; -- i
|
end loop; -- i
|
end if;
|
|
return tmp_v;
|
return tmp_v;
|
end function or_reduce_f;
|
end function or_reduce_f;
|
|
|
-- Function: AND-reduce all bits ----------------------------------------------------------
|
-- Function: AND-reduce all bits ----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function and_reduce_f(a : std_ulogic_vector) return std_ulogic is
|
function and_reduce_f(a : std_ulogic_vector) return std_ulogic is
|
variable tmp_v : std_ulogic;
|
variable tmp_v : std_ulogic;
|
begin
|
begin
|
tmp_v := '1';
|
tmp_v := '1';
|
if (a'low < a'high) then -- not null range?
|
for i in a'range loop
|
for i in a'low to a'high loop
|
|
tmp_v := tmp_v and a(i);
|
tmp_v := tmp_v and a(i);
|
end loop; -- i
|
end loop; -- i
|
end if;
|
|
return tmp_v;
|
return tmp_v;
|
end function and_reduce_f;
|
end function and_reduce_f;
|
|
|
-- Function: XOR-reduce all bits ----------------------------------------------------------
|
-- Function: XOR-reduce all bits ----------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function xor_reduce_f(a : std_ulogic_vector) return std_ulogic is
|
function xor_reduce_f(a : std_ulogic_vector) return std_ulogic is
|
variable tmp_v : std_ulogic;
|
variable tmp_v : std_ulogic;
|
begin
|
begin
|
tmp_v := '0';
|
tmp_v := '0';
|
if (a'low < a'high) then -- not null range?
|
for i in a'range loop
|
for i in a'low to a'high loop
|
|
tmp_v := tmp_v xor a(i);
|
tmp_v := tmp_v xor a(i);
|
end loop; -- i
|
end loop; -- i
|
end if;
|
|
return tmp_v;
|
return tmp_v;
|
end function xor_reduce_f;
|
end function xor_reduce_f;
|
|
|
-- Function: Convert std_ulogic_vector to hex char ----------------------------------------
|
-- Function: Convert std_ulogic_vector to hex char ----------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
