| Line 51... |
Line 51... |
-- "critical" number of implemented PMP regions --
|
-- "critical" number of implemented PMP regions --
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-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
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-- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
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-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
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-- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
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constant pmp_num_regions_critical_c : natural := 8; -- default=8
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constant pmp_num_regions_critical_c : natural := 8; -- default=8
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|
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-- "response time window" for processor-internal memories and IO devices
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-- "response time window" for processor-internal modules --
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constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
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constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)
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|
|
-- jtag tap - identifier --
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-- jtag tap - identifier --
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constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
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constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version
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constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
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constant jtag_tap_idcode_partid_c : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number
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constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
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constant jtag_tap_idcode_manid_c : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id
|
|
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- Architecture Constants (do not modify!) ------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
constant data_width_c : natural := 32; -- native data path width - do not change!
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constant data_width_c : natural := 32; -- native data path width - do not change!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060400"; -- no touchy!
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constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01060500"; -- no touchy!
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constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
constant archid_c : natural := 19; -- official NEORV32 architecture ID - hands off!
|
|
|
|
-- Check if we're inside the Matrix -------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
constant is_simulation_c : boolean := false -- seems like we're on real hardware
|
|
-- pragma translate_off
|
|
-- synthesis translate_off
|
|
-- synthesis synthesis_off
|
|
-- RTL_SYNTHESIS OFF
|
|
or true -- this MIGHT be a simulation
|
|
-- RTL_SYNTHESIS ON
|
|
-- synthesis synthesis_on
|
|
-- synthesis translate_on
|
|
-- pragma translate_on
|
|
;
|
|
|
-- External Interface Types ---------------------------------------------------------------
|
-- External Interface Types ---------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
|
type sdata_8x32r_t is array (0 to 7) of std_logic_vector(31 downto 0); -- resolved type
|
|
|
| Line 573... |
Line 587... |
constant csr_mhpmevent28_c : std_ulogic_vector(11 downto 0) := x"33c";
|
constant csr_mhpmevent28_c : std_ulogic_vector(11 downto 0) := x"33c";
|
constant csr_mhpmevent29_c : std_ulogic_vector(11 downto 0) := x"33d";
|
constant csr_mhpmevent29_c : std_ulogic_vector(11 downto 0) := x"33d";
|
constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := x"33e";
|
constant csr_mhpmevent30_c : std_ulogic_vector(11 downto 0) := x"33e";
|
constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := x"33f";
|
constant csr_mhpmevent31_c : std_ulogic_vector(11 downto 0) := x"33f";
|
-- machine trap handling --
|
-- machine trap handling --
|
constant csr_class_trap_c : std_ulogic_vector(08 downto 0) := x"34" & '0'; -- machine trap handling
|
constant csr_class_trap_c : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling
|
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340";
|
constant csr_mscratch_c : std_ulogic_vector(11 downto 0) := x"340";
|
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
|
constant csr_mepc_c : std_ulogic_vector(11 downto 0) := x"341";
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
|
constant csr_mcause_c : std_ulogic_vector(11 downto 0) := x"342";
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343";
|
constant csr_mtval_c : std_ulogic_vector(11 downto 0) := x"343";
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344";
|
constant csr_mip_c : std_ulogic_vector(11 downto 0) := x"344";
|
| Line 1087... |
Line 1101... |
port (
|
port (
|
-- global control --
|
-- global control --
|
clk_i : in std_ulogic; -- global clock, rising edge
|
clk_i : in std_ulogic; -- global clock, rising edge
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
rstn_i : in std_ulogic; -- global reset, low-active, async
|
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
|
sleep_o : out std_ulogic; -- cpu is in sleep mode when set
|
|
debug_o : out std_ulogic; -- cpu is in debug mode when set
|
-- instruction bus interface --
|
-- instruction bus interface --
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_addr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_rdata_i : in std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_wdata_o : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
i_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
| Line 1614... |
Line 1629... |
end component;
|
end component;
|
|
|
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
|
-- Component: Watchdog Timer (WDT) --------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
component neorv32_wdt
|
component neorv32_wdt
|
|
generic (
|
|
DEBUG_EN : boolean -- CPU debug mode implemented?
|
|
);
|
port (
|
port (
|
-- host access --
|
-- host access --
|
clk_i : in std_ulogic; -- global clock line
|
clk_i : in std_ulogic; -- global clock line
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rstn_i : in std_ulogic; -- global reset line, low-active
|
rden_i : in std_ulogic; -- read enable
|
rden_i : in std_ulogic; -- read enable
|
wren_i : in std_ulogic; -- write enable
|
wren_i : in std_ulogic; -- write enable
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
addr_i : in std_ulogic_vector(31 downto 0); -- address
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_i : in std_ulogic_vector(31 downto 0); -- data in
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
data_o : out std_ulogic_vector(31 downto 0); -- data out
|
ack_o : out std_ulogic; -- transfer acknowledge
|
ack_o : out std_ulogic; -- transfer acknowledge
|
|
-- CPU in debug mode? --
|
|
cpu_debug_i : in std_ulogic;
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_en_o : out std_ulogic; -- enable clock generator
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
clkgen_i : in std_ulogic_vector(07 downto 0);
|
-- timeout event --
|
-- timeout event --
|
irq_o : out std_ulogic; -- timeout IRQ
|
irq_o : out std_ulogic; -- timeout IRQ
|
| Line 2088... |
Line 2108... |
|
|
end neorv32_package;
|
end neorv32_package;
|
|
|
package body neorv32_package is
|
package body neorv32_package is
|
|
|
-- Function: Minimal required number of bits to represent input number --------------------
|
-- Function: Minimal required number of bits to represent <input> numbers -----------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
function index_size_f(input : natural) return natural is
|
function index_size_f(input : natural) return natural is
|
begin
|
begin
|
for i in 0 to natural'high loop
|
for i in 0 to natural'high loop
|
if (2**i >= input) then
|
if (2**i >= input) then
|
