| Line 93... |
Line 93... |
constant ctrl_tx_size_lsb_c : natural := 12; -- r/-: log2(TX FIFO size)
|
constant ctrl_tx_size_lsb_c : natural := 12; -- r/-: log2(TX FIFO size)
|
constant ctrl_tx_size_msb_c : natural := 15;
|
constant ctrl_tx_size_msb_c : natural := 15;
|
--
|
--
|
constant ctrl_en_c : natural := 31; -- r/w: global enable
|
constant ctrl_en_c : natural := 31; -- r/w: global enable
|
|
|
|
-- interrupt configuration register bits --
|
|
constant irq_rx_en_lsb_c : natural := 0; -- r/w: enable RX interrupt for link 0..7
|
|
constant irq_rx_en_msb_c : natural := 7;
|
|
--
|
|
constant irq_rx_mode_lsb_c : natural := 8; -- r/w: RX IRQ mode: 0=FIFO at least half-full; 1=FIFO not empty
|
|
constant irq_rx_mode_msb_c : natural := 15;
|
|
--
|
|
constant irq_tx_en_lsb_c : natural := 16; -- r/w: enable TX interrupt for link 0..7
|
|
constant irq_tx_en_msb_c : natural := 23;
|
|
--
|
|
constant irq_tx_mode_lsb_c : natural := 24; -- r/w: TX IRQ mode: 0=FIFO less than half-full; 1=FIFO not full
|
|
constant irq_tx_mode_msb_c : natural := 31;
|
|
|
-- status register bits --
|
-- status register bits --
|
constant status_rx_avail_lsb_c : natural := 0; -- r/-: set if TX link 0..7 is ready to send
|
constant status_rx_avail_lsb_c : natural := 0; -- r/-: set if RX link 0..7 FIFO is NOT empty
|
constant status_rx_avail_msb_c : natural := 7;
|
constant status_rx_avail_msb_c : natural := 7;
|
--
|
--
|
constant status_tx_free_lsb_c : natural := 8; -- r/-: set if RX link 0..7 data available
|
constant status_tx_free_lsb_c : natural := 8; -- r/-: set if TX link 0..7 FIFO is NOT full
|
constant status_tx_free_msb_c : natural := 15;
|
constant status_tx_free_msb_c : natural := 15;
|
--
|
--
|
constant status_rx_half_lsb_c : natural := 16; -- r/-: set if TX link 0..7 FIFO fill-level is >= half-full
|
constant status_rx_half_lsb_c : natural := 16; -- r/-: set if RX link 0..7 FIFO fill-level is >= half-full
|
constant status_rx_half_msb_c : natural := 23;
|
constant status_rx_half_msb_c : natural := 23;
|
--
|
--
|
constant status_tx_half_lsb_c : natural := 24; -- r/-: set if RX link 0..7 FIFO fill-level is > half-full
|
constant status_tx_half_lsb_c : natural := 24; -- r/-: set if TX link 0..7 FIFO fill-level is > half-full
|
constant status_tx_half_msb_c : natural := 31;
|
constant status_tx_half_msb_c : natural := 31;
|
|
|
-- bus access control --
|
-- bus access control --
|
signal ack_read : std_ulogic;
|
signal ack_read : std_ulogic;
|
signal ack_write : std_ulogic;
|
signal ack_write : std_ulogic;
|
| Line 115... |
Line 128... |
signal addr : std_ulogic_vector(31 downto 0);
|
signal addr : std_ulogic_vector(31 downto 0);
|
|
|
-- control register --
|
-- control register --
|
signal enable : std_ulogic; -- global enable
|
signal enable : std_ulogic; -- global enable
|
|
|
|
-- IRQ configuration register --
|
|
signal irq_rx_en : std_ulogic_vector(7 downto 0);
|
|
signal irq_rx_mode : std_ulogic_vector(7 downto 0);
|
|
signal irq_tx_en : std_ulogic_vector(7 downto 0);
|
|
signal irq_tx_mode : std_ulogic_vector(7 downto 0);
|
|
|
-- stream link fifo interface --
|
-- stream link fifo interface --
|
type fifo_data_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type fifo_data_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
|
type fifo_rx_level_t is array (0 to 7) of std_ulogic_vector(index_size_f(SLINK_RX_FIFO) downto 0);
|
|
type fifo_tx_level_t is array (0 to 7) of std_ulogic_vector(index_size_f(SLINK_TX_FIFO) downto 0);
|
|
signal rx_fifo_rdata : fifo_data_t;
|
signal rx_fifo_rdata : fifo_data_t;
|
signal rx_fifo_level : fifo_rx_level_t;
|
|
signal tx_fifo_level : fifo_tx_level_t;
|
|
signal fifo_clear : std_ulogic;
|
signal fifo_clear : std_ulogic;
|
signal link_sel : std_ulogic_vector(7 downto 0);
|
signal link_sel : std_ulogic_vector(7 downto 0);
|
signal tx_fifo_we, rx_fifo_re : std_ulogic_vector(7 downto 0);
|
signal tx_fifo_we : std_ulogic_vector(7 downto 0);
|
signal rx_fifo_avail, rx_fifo_avail_ff : std_ulogic_vector(7 downto 0);
|
signal rx_fifo_re : std_ulogic_vector(7 downto 0);
|
signal tx_fifo_free, tx_fifo_free_ff : std_ulogic_vector(7 downto 0);
|
signal rx_fifo_avail : std_ulogic_vector(7 downto 0);
|
signal rx_fifo_half, rx_fifo_half_ff : std_ulogic_vector(7 downto 0);
|
signal tx_fifo_free : std_ulogic_vector(7 downto 0);
|
signal tx_fifo_half, tx_fifo_half_ff : std_ulogic_vector(7 downto 0);
|
signal rx_fifo_half : std_ulogic_vector(7 downto 0);
|
|
signal tx_fifo_half : std_ulogic_vector(7 downto 0);
|
-- interrupt controller --
|
|
type irq_t is record
|
|
rx_pending : std_ulogic;
|
|
rx_pending_ff : std_ulogic;
|
|
rx_fire : std_ulogic;
|
|
tx_pending : std_ulogic;
|
|
tx_pending_ff : std_ulogic;
|
|
tx_fire : std_ulogic;
|
|
wr_ack : std_ulogic;
|
|
rd_ack : std_ulogic;
|
|
end record;
|
|
signal irq : irq_t;
|
|
|
|
begin
|
begin
|
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 172... |
Line 175... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
rw_access: process(clk_i)
|
rw_access: process(clk_i)
|
begin
|
begin
|
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- write access --
|
-- write access --
|
irq.wr_ack <= '0';
|
|
ack_write <= '0';
|
ack_write <= '0';
|
if (acc_en = '1') and (wren_i = '1') then
|
if (acc_en = '1') and (wren_i = '1') then
|
if (addr(5) = '0') then -- control/status
|
if (addr(5) = '0') then -- control/status/irq
|
if (addr(4) = '0') then -- control register
|
if (addr(4 downto 3) = "00") then -- control register
|
enable <= data_i(ctrl_en_c);
|
enable <= data_i(ctrl_en_c);
|
else -- status register
|
end if;
|
irq.wr_ack <= '1';
|
if (addr(4 downto 3) = "01") then -- IRQ configuration register
|
|
for i in 0 to SLINK_NUM_RX-1 loop
|
|
irq_rx_en(i) <= data_i(i + irq_rx_en_lsb_c);
|
|
irq_rx_mode(i) <= data_i(i + irq_rx_mode_lsb_c);
|
|
end loop;
|
|
for i in 0 to SLINK_NUM_TX-1 loop
|
|
irq_tx_en(i) <= data_i(i + irq_tx_en_lsb_c);
|
|
irq_tx_mode(i) <= data_i(i + irq_tx_mode_lsb_c);
|
|
end loop;
|
end if;
|
end if;
|
ack_write <= '1';
|
ack_write <= '1';
|
else -- TX links
|
else -- TX links
|
ack_write <= or_reduce_f(link_sel and tx_fifo_free);
|
ack_write <= or_reduce_f(link_sel and tx_fifo_free);
|
end if;
|
end if;
|
end if;
|
end if;
|
|
|
-- read access --
|
-- read access --
|
irq.rd_ack <= '0';
|
|
data_o <= (others => '0');
|
data_o <= (others => '0');
|
ack_read <= '0';
|
ack_read <= '0';
|
if (acc_en = '1') and (rden_i = '1') then
|
if (acc_en = '1') and (rden_i = '1') then
|
if (addr(5) = '0') then -- control/status registers
|
if (addr(5) = '0') then -- control/status registers
|
ack_read <= '1';
|
ack_read <= '1';
|
if (addr(4) = '0') then -- control register
|
case addr(4 downto 3) is
|
|
when "00" => -- control register
|
data_o(ctrl_rx_num_msb_c downto ctrl_rx_num_lsb_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_RX, 4));
|
data_o(ctrl_rx_num_msb_c downto ctrl_rx_num_lsb_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_RX, 4));
|
data_o(ctrl_tx_num_msb_c downto ctrl_tx_num_lsb_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_TX, 4));
|
data_o(ctrl_tx_num_msb_c downto ctrl_tx_num_lsb_c) <= std_ulogic_vector(to_unsigned(SLINK_NUM_TX, 4));
|
data_o(ctrl_rx_size_msb_c downto ctrl_rx_size_lsb_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_RX_FIFO), 4));
|
data_o(ctrl_rx_size_msb_c downto ctrl_rx_size_lsb_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_RX_FIFO), 4));
|
data_o(ctrl_tx_size_msb_c downto ctrl_tx_size_lsb_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_TX_FIFO), 4));
|
data_o(ctrl_tx_size_msb_c downto ctrl_tx_size_lsb_c) <= std_ulogic_vector(to_unsigned(index_size_f(SLINK_TX_FIFO), 4));
|
data_o(ctrl_en_c) <= enable;
|
data_o(ctrl_en_c) <= enable;
|
else -- fifo status register
|
when "01" => -- IRQ configuration register
|
|
for i in 0 to SLINK_NUM_RX-1 loop
|
|
data_o(irq_rx_en_lsb_c + i) <= irq_rx_en(i);
|
|
data_o(irq_rx_mode_lsb_c + i) <= irq_rx_mode(i) or bool_to_ulogic_f(boolean(SLINK_RX_FIFO = 1)); -- tie to one if SLINK_RX_FIFO is 1
|
|
end loop;
|
|
for i in 0 to SLINK_NUM_TX-1 loop
|
|
data_o(irq_tx_en_lsb_c + i) <= irq_tx_en(i);
|
|
data_o(irq_tx_mode_lsb_c + i) <= irq_tx_mode(i) or bool_to_ulogic_f(boolean(SLINK_TX_FIFO = 1)); -- tie to one if SLINK_TX_FIFO is 1
|
|
end loop;
|
|
when "10" | "11" => -- fifo status register
|
data_o(status_rx_avail_msb_c downto status_rx_avail_lsb_c) <= rx_fifo_avail;
|
data_o(status_rx_avail_msb_c downto status_rx_avail_lsb_c) <= rx_fifo_avail;
|
data_o(status_tx_free_msb_c downto status_tx_free_lsb_c) <= tx_fifo_free;
|
data_o(status_tx_free_msb_c downto status_tx_free_lsb_c) <= tx_fifo_free;
|
data_o(status_rx_half_msb_c downto status_rx_half_lsb_c) <= rx_fifo_half;
|
data_o(status_rx_half_msb_c downto status_rx_half_lsb_c) <= rx_fifo_half;
|
data_o(status_tx_half_msb_c downto status_tx_half_lsb_c) <= tx_fifo_half;
|
data_o(status_tx_half_msb_c downto status_tx_half_lsb_c) <= tx_fifo_half;
|
irq.rd_ack <= '1';
|
when others =>
|
end if;
|
data_o <= (others => '0');
|
|
end case;
|
else -- RX links
|
else -- RX links
|
data_o <= rx_fifo_rdata(to_integer(unsigned(addr(4 downto 2))));
|
data_o <= rx_fifo_rdata(to_integer(unsigned(addr(4 downto 2))));
|
ack_read <= or_reduce_f(link_sel and rx_fifo_avail);
|
ack_read <= or_reduce_f(link_sel and rx_fifo_avail);
|
end if;
|
end if;
|
end if;
|
end if;
|
| Line 222... |
Line 242... |
|
|
-- link fifo reset (sync) --
|
-- link fifo reset (sync) --
|
fifo_clear <= not enable;
|
fifo_clear <= not enable;
|
|
|
|
|
-- FIFO Level Monitoring ------------------------------------------------------------------
|
-- Interrupt Generator --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
level_monitor: process(rx_fifo_level, tx_fifo_level)
|
irq_arbiter: process(clk_i)
|
|
variable rx_tmp_v : std_ulogic_vector(SLINK_NUM_RX-1 downto 0);
|
|
variable tx_tmp_v : std_ulogic_vector(SLINK_NUM_TX-1 downto 0);
|
begin
|
begin
|
-- RX FIFO --
|
if rising_edge(clk_i) then
|
rx_fifo_half <= (others => '0');
|
if (enable = '0') then -- no interrupts if unit is disabled
|
|
irq_rx_o <= '0';
|
|
irq_tx_o <= '0';
|
|
else
|
|
|
|
-- RX interrupt --
|
|
if (SLINK_RX_FIFO = 1) then
|
|
irq_rx_o <= or_reduce_f(irq_rx_en and rx_fifo_avail); -- fire if any RX_FIFO is not empty
|
|
else
|
|
rx_tmp_v := (others => '0');
|
for i in 0 to SLINK_NUM_RX-1 loop
|
for i in 0 to SLINK_NUM_RX-1 loop
|
if (unsigned(rx_fifo_level(i)) >= to_unsigned(cond_sel_natural_f(boolean(SLINK_RX_FIFO > 1), SLINK_RX_FIFO/2, 1), rx_fifo_level(i)'length)) then
|
if (irq_rx_mode(i) = '0') then -- fire if any RX_FIFO is at least half-full
|
rx_fifo_half(i) <= '1';
|
rx_tmp_v(i) := rx_fifo_half(i);
|
|
else -- fire if any RX_FIFO is not empty (= data available)
|
|
rx_tmp_v(i) := rx_fifo_avail(i);
|
end if;
|
end if;
|
end loop;
|
end loop;
|
-- TX FIFO --
|
irq_rx_o <= or_reduce_f(irq_rx_en and rx_tmp_v);
|
tx_fifo_half <= (others => '0');
|
|
for i in 0 to SLINK_NUM_TX-1 loop
|
|
if (unsigned(tx_fifo_level(i)) >= to_unsigned(cond_sel_natural_f(boolean(SLINK_TX_FIFO > 1), SLINK_TX_FIFO/2, 1), tx_fifo_level(i)'length)) then
|
|
tx_fifo_half(i) <= '1';
|
|
end if;
|
end if;
|
end loop;
|
|
end process level_monitor;
|
|
|
|
|
-- TX interrupt --
|
-- Interrupt Generator --------------------------------------------------------------------
|
if (SLINK_TX_FIFO = 1) then
|
-- -------------------------------------------------------------------------------------------
|
irq_tx_o <= or_reduce_f(irq_tx_en and tx_fifo_free); -- fire if any TX_FIFO is not full
|
irq_arbiter: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
if (enable = '0') then
|
|
irq.rx_pending <= '0';
|
|
irq.tx_pending <= '0';
|
|
else
|
else
|
-- RX IRQ --
|
tx_tmp_v := (others => '0');
|
if (irq.rx_pending = '0') then
|
for i in 0 to SLINK_NUM_TX-1 loop
|
irq.rx_pending <= irq.rx_fire;
|
if (irq_tx_mode(i) = '0') then -- fire if any RX_FIFO is less than half-full
|
elsif (irq.rd_ack = '1') or (irq.wr_ack = '1') then
|
tx_tmp_v(i) := not rx_fifo_half(i);
|
irq.rx_pending <= '0';
|
else -- fire if any RX_FIFO is not full (= free buffer space available)
|
end if;
|
tx_tmp_v(i) := tx_fifo_free(i);
|
-- TX IRQ --
|
end if;
|
if (irq.tx_pending = '0') then
|
end loop;
|
irq.tx_pending <= irq.tx_fire;
|
irq_tx_o <= or_reduce_f(irq_tx_en and tx_tmp_v);
|
elsif (irq.rd_ack = '1') or (irq.wr_ack = '1') then
|
end if;
|
irq.tx_pending <= '0';
|
end if;
|
end if;
|
|
end if;
|
|
-- CPU IRQs --
|
|
irq.rx_pending_ff <= irq.rx_pending;
|
|
irq.tx_pending_ff <= irq.tx_pending;
|
|
irq_rx_o <= irq.rx_pending and (not irq.rx_pending_ff);
|
|
irq_tx_o <= irq.tx_pending and (not irq.tx_pending_ff);
|
|
end if;
|
end if;
|
end process irq_arbiter;
|
end process irq_arbiter;
|
|
|
-- status buffer --
|
|
irq_generator_sync: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
rx_fifo_avail_ff <= rx_fifo_avail;
|
|
rx_fifo_half_ff <= rx_fifo_half;
|
|
tx_fifo_free_ff <= tx_fifo_free;
|
|
tx_fifo_half_ff <= tx_fifo_half;
|
|
end if;
|
|
end process irq_generator_sync;
|
|
|
|
-- IRQ event detector --
|
|
-- RX interrupt: fire if any RX_FIFO gets full / fire if any RX_FIFO.level becomes half-full
|
|
irq.rx_fire <= or_reduce_f(rx_fifo_avail and (not rx_fifo_avail_ff)) when (SLINK_RX_FIFO = 1) else or_reduce_f(rx_fifo_half and (not rx_fifo_half_ff));
|
|
-- TX interrupt: fire if any TX_FIFO gets empty / fire if any TX_FIFO.level falls below half-full level
|
|
irq.tx_fire <= or_reduce_f(tx_fifo_free and (not tx_fifo_free_ff)) when (SLINK_TX_FIFO = 1) else or_reduce_f((not tx_fifo_half) and tx_fifo_half_ff);
|
|
|
|
|
|
-- Link Select ----------------------------------------------------------------------------
|
-- Link Select ----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
link_select: process(addr)
|
link_select: process(addr)
|
begin
|
begin
|
| Line 323... |
Line 320... |
for i in 0 to SLINK_NUM_TX-1 generate
|
for i in 0 to SLINK_NUM_TX-1 generate
|
transmit_fifo_inst: neorv32_fifo
|
transmit_fifo_inst: neorv32_fifo
|
generic map (
|
generic map (
|
FIFO_DEPTH => SLINK_TX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
FIFO_DEPTH => SLINK_TX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
FIFO_WIDTH => 32, -- size of data elements in fifo
|
FIFO_WIDTH => 32, -- size of data elements in fifo
|
FIFO_RSYNC => false, -- false = async read; true = sync read
|
FIFO_RSYNC => false, -- async read
|
FIFO_SAFE => true -- true = allow read/write only if entry available
|
FIFO_SAFE => true -- safe access
|
)
|
)
|
port map (
|
port map (
|
-- control --
|
-- control --
|
clk_i => clk_i, -- clock, rising edge
|
clk_i => clk_i, -- clock, rising edge
|
rstn_i => '1', -- async reset, low-active
|
rstn_i => '1', -- async reset, low-active
|
clear_i => fifo_clear, -- sync reset, high-active
|
clear_i => fifo_clear, -- sync reset, high-active
|
level_o => tx_fifo_level(i), -- fill level
|
level_o => open, -- fill level
|
|
half_o => tx_fifo_half(i), -- FIFO is at least half full
|
-- write port --
|
-- write port --
|
wdata_i => data_i, -- write data
|
wdata_i => data_i, -- write data
|
we_i => tx_fifo_we(i), -- write enable
|
we_i => tx_fifo_we(i), -- write enable
|
free_o => tx_fifo_free(i), -- at least one entry is free when set
|
free_o => tx_fifo_free(i), -- at least one entry is free when set
|
-- read port --
|
-- read port --
|
| Line 349... |
Line 347... |
transmit_fifo_gen_terminate:
|
transmit_fifo_gen_terminate:
|
for i in SLINK_NUM_TX to 7 generate
|
for i in SLINK_NUM_TX to 7 generate
|
tx_fifo_free(i) <= '0';
|
tx_fifo_free(i) <= '0';
|
slink_tx_dat_o(i) <= (others => '0');
|
slink_tx_dat_o(i) <= (others => '0');
|
slink_tx_val_o(i) <= '0';
|
slink_tx_val_o(i) <= '0';
|
tx_fifo_level(i) <= (others => '0');
|
tx_fifo_half(i) <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
-- RX Link FIFOs --------------------------------------------------------------------------
|
-- RX Link FIFOs --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 361... |
Line 359... |
for i in 0 to SLINK_NUM_RX-1 generate
|
for i in 0 to SLINK_NUM_RX-1 generate
|
receive_fifo_inst: neorv32_fifo
|
receive_fifo_inst: neorv32_fifo
|
generic map (
|
generic map (
|
FIFO_DEPTH => SLINK_RX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
FIFO_DEPTH => SLINK_RX_FIFO, -- number of fifo entries; has to be a power of two; min 1
|
FIFO_WIDTH => 32, -- size of data elements in fifo
|
FIFO_WIDTH => 32, -- size of data elements in fifo
|
FIFO_RSYNC => false, -- false = async read; true = sync read
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FIFO_RSYNC => false, -- async read
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FIFO_SAFE => true -- true = allow read/write only if entry available
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FIFO_SAFE => true -- safe access
|
)
|
)
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port map (
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port map (
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-- control --
|
-- control --
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clk_i => clk_i, -- clock, rising edge
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clk_i => clk_i, -- clock, rising edge
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rstn_i => '1', -- async reset, low-active
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rstn_i => '1', -- async reset, low-active
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clear_i => fifo_clear, -- sync reset, high-active
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clear_i => fifo_clear, -- sync reset, high-active
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level_o => rx_fifo_level(i), -- fill level
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level_o => open, -- fill level
|
|
half_o => rx_fifo_half(i), -- FIFO is at least half full
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-- write port --
|
-- write port --
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wdata_i => slink_rx_dat_i(i), -- write data
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wdata_i => slink_rx_dat_i(i), -- write data
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we_i => slink_rx_val_i(i), -- write enable
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we_i => slink_rx_val_i(i), -- write enable
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free_o => slink_rx_rdy_o(i), -- at least one entry is free when set
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free_o => slink_rx_rdy_o(i), -- at least one entry is free when set
|
-- read port --
|
-- read port --
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| Line 387... |
Line 386... |
receive_fifo_gen_terminate:
|
receive_fifo_gen_terminate:
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for i in SLINK_NUM_RX to 7 generate
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for i in SLINK_NUM_RX to 7 generate
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rx_fifo_avail(i) <= '0';
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rx_fifo_avail(i) <= '0';
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slink_rx_rdy_o(i) <= '0';
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slink_rx_rdy_o(i) <= '0';
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rx_fifo_rdata(i) <= (others => '0');
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rx_fifo_rdata(i) <= (others => '0');
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rx_fifo_level(i) <= (others => '0');
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rx_fifo_half(i) <= '0';
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end generate;
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end generate;
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|
|
|
|
end neorv32_slink_rtl;
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end neorv32_slink_rtl;
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No newline at end of file
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No newline at end of file
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