| Line 5... |
Line 5... |
-- # 8 clock speeds (derived from system clock), 8 dedicated chip-select lines (low-active). #
|
-- # 8 clock speeds (derived from system clock), 8 dedicated chip-select lines (low-active). #
|
-- # Interrupt: SPI_transfer_done #
|
-- # Interrupt: SPI_transfer_done #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # Redistribution and use in source and binary forms, with or without modification, are #
|
-- # permitted provided that the following conditions are met: #
|
-- # permitted provided that the following conditions are met: #
|
-- # #
|
-- # #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
|
| Line 60... |
Line 60... |
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- interrupt --
|
-- interrupt --
|
spi_irq_o : out std_ulogic -- transmission done interrupt
|
irq_o : out std_ulogic -- transmission done interrupt
|
);
|
);
|
end neorv32_spi;
|
end neorv32_spi;
|
|
|
architecture neorv32_spi_rtl of neorv32_spi is
|
architecture neorv32_spi_rtl of neorv32_spi is
|
|
|
| Line 87... |
Line 87... |
constant ctrl_spi_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0
|
constant ctrl_spi_prsc0_c : natural := 10; -- r/w: spi prescaler select bit 0
|
constant ctrl_spi_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1
|
constant ctrl_spi_prsc1_c : natural := 11; -- r/w: spi prescaler select bit 1
|
constant ctrl_spi_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2
|
constant ctrl_spi_prsc2_c : natural := 12; -- r/w: spi prescaler select bit 2
|
constant ctrl_spi_size0_c : natural := 13; -- r/w: data size (00: 8-bit, 01: 16-bit)
|
constant ctrl_spi_size0_c : natural := 13; -- r/w: data size (00: 8-bit, 01: 16-bit)
|
constant ctrl_spi_size1_c : natural := 14; -- r/w: data size (10: 24-bit, 11: 32-bit)
|
constant ctrl_spi_size1_c : natural := 14; -- r/w: data size (10: 24-bit, 11: 32-bit)
|
constant ctrl_spi_irq_en_c : natural := 15; -- r/w: spi transmission done interrupt enable
|
|
--
|
--
|
constant ctrl_spi_busy_c : natural := 31; -- r/-: spi transceiver is busy
|
constant ctrl_spi_busy_c : natural := 31; -- r/-: spi transceiver is busy
|
|
|
-- access control --
|
-- access control --
|
signal acc_en : std_ulogic; -- module access enable
|
signal acc_en : std_ulogic; -- module access enable
|
signal addr : std_ulogic_vector(31 downto 0); -- access address
|
signal addr : std_ulogic_vector(31 downto 0); -- access address
|
signal wren : std_ulogic; -- word write enable
|
signal wren : std_ulogic; -- word write enable
|
signal rden : std_ulogic; -- read enable
|
signal rden : std_ulogic; -- read enable
|
|
|
-- accessible regs --
|
-- accessible regs --
|
signal ctrl : std_ulogic_vector(15 downto 0);
|
signal ctrl : std_ulogic_vector(14 downto 0);
|
signal tx_data_reg : std_ulogic_vector(31 downto 0);
|
signal tx_data_reg : std_ulogic_vector(31 downto 0);
|
signal rx_data : std_ulogic_vector(31 downto 0);
|
signal rx_data : std_ulogic_vector(31 downto 0);
|
|
|
-- clock generator --
|
-- clock generator --
|
signal spi_clk : std_ulogic;
|
signal spi_clk : std_ulogic;
|
| Line 164... |
Line 163... |
data_o(ctrl_spi_prsc0_c) <= ctrl(ctrl_spi_prsc0_c);
|
data_o(ctrl_spi_prsc0_c) <= ctrl(ctrl_spi_prsc0_c);
|
data_o(ctrl_spi_prsc1_c) <= ctrl(ctrl_spi_prsc1_c);
|
data_o(ctrl_spi_prsc1_c) <= ctrl(ctrl_spi_prsc1_c);
|
data_o(ctrl_spi_prsc2_c) <= ctrl(ctrl_spi_prsc2_c);
|
data_o(ctrl_spi_prsc2_c) <= ctrl(ctrl_spi_prsc2_c);
|
data_o(ctrl_spi_size0_c) <= ctrl(ctrl_spi_size0_c);
|
data_o(ctrl_spi_size0_c) <= ctrl(ctrl_spi_size0_c);
|
data_o(ctrl_spi_size1_c) <= ctrl(ctrl_spi_size1_c);
|
data_o(ctrl_spi_size1_c) <= ctrl(ctrl_spi_size1_c);
|
data_o(ctrl_spi_irq_en_c) <= ctrl(ctrl_spi_irq_en_c);
|
|
--
|
--
|
data_o(ctrl_spi_busy_c) <= spi_busy;
|
data_o(ctrl_spi_busy_c) <= spi_busy;
|
else -- spi_rtx_addr_c
|
else -- spi_rtx_addr_c
|
data_o <= rx_data;
|
data_o <= rx_data;
|
end if;
|
end if;
|
| Line 197... |
Line 195... |
-- input (sdi) synchronizer --
|
-- input (sdi) synchronizer --
|
spi_sdi_ff0 <= spi_sdi_i;
|
spi_sdi_ff0 <= spi_sdi_i;
|
spi_sdi_ff1 <= spi_sdi_ff0;
|
spi_sdi_ff1 <= spi_sdi_ff0;
|
|
|
-- serial engine --
|
-- serial engine --
|
spi_irq_o <= '0';
|
irq_o <= '0';
|
if (spi_state0 = '0') or (ctrl(ctrl_spi_en_c) = '0') then -- idle or disabled
|
if (spi_state0 = '0') or (ctrl(ctrl_spi_en_c) = '0') then -- idle or disabled
|
-- --------------------------------------------------------------
|
-- --------------------------------------------------------------
|
spi_bitcnt <= (others => '0');
|
spi_bitcnt <= (others => '0');
|
spi_state1 <= '0';
|
spi_state1 <= '0';
|
spi_sdo_o <= '0';
|
spi_sdo_o <= '0';
|
| Line 245... |
Line 243... |
spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1;
|
spi_rtx_sreg <= spi_rtx_sreg(30 downto 0) & spi_sdi_ff1;
|
end if;
|
end if;
|
if (spi_bitcnt = spi_bitcnt_max) then
|
if (spi_bitcnt = spi_bitcnt_max) then
|
spi_state0 <= '0';
|
spi_state0 <= '0';
|
spi_busy <= '0';
|
spi_busy <= '0';
|
spi_irq_o <= ctrl(ctrl_spi_irq_en_c);
|
irq_o <= '1';
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
