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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_sysinfo.vhd] - Diff between revs 40 and 41

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Rev 40 Rev 41
Line 53... Line 53...
    MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
    MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
    MEM_INT_IMEM_ROM  : boolean := false;  -- implement processor-internal instruction memory as ROM
    MEM_INT_IMEM_ROM  : boolean := false;  -- implement processor-internal instruction memory as ROM
    -- Internal Data memory --
    -- Internal Data memory --
    MEM_INT_DMEM_USE  : boolean := true;   -- implement processor-internal data memory
    MEM_INT_DMEM_USE  : boolean := true;   -- implement processor-internal data memory
    MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
    MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
 
    -- Internal Cache memory --
 
    ICACHE_USE           : boolean := true;   -- implement instruction cache
 
    ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
 
    ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
 
    ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
    -- External memory interface --
    -- External memory interface --
    MEM_EXT_USE       : boolean := false;  -- implement external memory bus interface?
    MEM_EXT_USE       : boolean := false;  -- implement external memory bus interface?
    -- Processor peripherals --
    -- Processor peripherals --
    IO_GPIO_USE       : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
    IO_GPIO_USE       : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
    IO_MTIME_USE      : boolean := true;   -- implement machine system timer (MTIME)?
    IO_MTIME_USE      : boolean := true;   -- implement machine system timer (MTIME)?
Line 120... Line 125...
  sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_USE);       -- external memory bus interface implemented?
  sysinfo_mem(2)(01) <= bool_to_ulogic_f(MEM_EXT_USE);       -- external memory bus interface implemented?
  sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE);  -- processor-internal instruction memory implemented?
  sysinfo_mem(2)(02) <= bool_to_ulogic_f(MEM_INT_IMEM_USE);  -- processor-internal instruction memory implemented?
  sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM);  -- processor-internal instruction memory implemented as ROM?
  sysinfo_mem(2)(03) <= bool_to_ulogic_f(MEM_INT_IMEM_ROM);  -- processor-internal instruction memory implemented as ROM?
  sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE);  -- processor-internal data memory implemented?
  sysinfo_mem(2)(04) <= bool_to_ulogic_f(MEM_INT_DMEM_USE);  -- processor-internal data memory implemented?
  sysinfo_mem(2)(05) <= bool_to_ulogic_f(xbus_big_endian_c); -- is external memory bus interface using BIG-endian byte-order?
  sysinfo_mem(2)(05) <= bool_to_ulogic_f(xbus_big_endian_c); -- is external memory bus interface using BIG-endian byte-order?
 
  sysinfo_mem(2)(06) <= bool_to_ulogic_f(ICACHE_USE);        -- processor-internal instruction cache implemented?
  --
  --
  sysinfo_mem(2)(15 downto 06) <= (others => '0'); -- reserved
  sysinfo_mem(2)(15 downto 07) <= (others => '0'); -- reserved
  -- IO --
  -- IO --
  sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE);  -- general purpose input/output port unit (GPIO) implemented?
  sysinfo_mem(2)(16) <= bool_to_ulogic_f(IO_GPIO_USE);  -- general purpose input/output port unit (GPIO) implemented?
  sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- machine system timer (MTIME) implemented?
  sysinfo_mem(2)(17) <= bool_to_ulogic_f(IO_MTIME_USE); -- machine system timer (MTIME) implemented?
  sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_USE);  -- universal asynchronous receiver/transmitter (UART) implemented?
  sysinfo_mem(2)(18) <= bool_to_ulogic_f(IO_UART_USE);  -- universal asynchronous receiver/transmitter (UART) implemented?
  sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_USE);   -- serial peripheral interface (SPI) implemented?
  sysinfo_mem(2)(19) <= bool_to_ulogic_f(IO_SPI_USE);   -- serial peripheral interface (SPI) implemented?
Line 136... Line 142...
  sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE);  -- true random number generator (TRNG) implemented?
  sysinfo_mem(2)(24) <= bool_to_ulogic_f(IO_TRNG_USE);  -- true random number generator (TRNG) implemented?
  sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_CFU1_USE);  -- custom functions unit 1 (CFU1) implemented?
  sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_CFU1_USE);  -- custom functions unit 1 (CFU1) implemented?
  --
  --
  sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved
  sysinfo_mem(2)(31 downto 26) <= (others => '0'); -- reserved
 
 
  -- SYSINFO(3): reserved --
  -- SYSINFO(3): Cache configuration --
  sysinfo_mem(3) <= (others => '0'); -- reserved
  sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4))    when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
 
  sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4))    when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(number_of_block)
 
  sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_USE = true) else (others => '0'); -- i-cache: log2(associativity)
 
  sysinfo_mem(3)(15 downto 12) <= (others => '0'); -- replacement strategy (irrelevant since i-cache is read-only)
 
  --
 
  sysinfo_mem(3)(19 downto 16) <= (others => '0'); -- reserved (for d-cache.block_size)
 
  sysinfo_mem(3)(23 downto 20) <= (others => '0'); -- reserved (for d-cache.num_blocks)
 
  sysinfo_mem(3)(27 downto 24) <= (others => '0'); -- reserved (for d-cache.associativity)
 
  sysinfo_mem(3)(31 downto 28) <= (others => '0'); -- reserved (for d-cache.replacement_Strategy)
 
 
  -- SYSINFO(4): Base address of instruction memory space --
  -- SYSINFO(4): Base address of instruction memory space --
  sysinfo_mem(4) <= ispace_base_c; -- defined in neorv32_package.vhd file
  sysinfo_mem(4) <= ispace_base_c; -- defined in neorv32_package.vhd file
 
 
  -- SYSINFO(5): Base address of data memory space --
  -- SYSINFO(5): Base address of data memory space --

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