| Line 4... |
Line 4... |
-- # This unit provides information regarding the NEORV32 processor system configuration - #
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-- # This unit provides information regarding the NEORV32 processor system configuration - #
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-- # mostly derived from the top's configuration generics. #
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-- # mostly derived from the top's configuration generics. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 89... |
Line 89... |
IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
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IO_TRNG_EN : boolean; -- implement true random number generator (TRNG)?
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IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
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IO_CFS_EN : boolean; -- implement custom functions subsystem (CFS)?
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IO_SLINK_EN : boolean; -- implement stream link interface?
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IO_SLINK_EN : boolean; -- implement stream link interface?
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IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN : boolean; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
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IO_XIRQ_NUM_CH : natural; -- number of external interrupt (XIRQ) channels to implement
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IO_GPTMR_EN : boolean -- implement general purpose timer (GPTMR)?
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IO_GPTMR_EN : boolean; -- implement general purpose timer (GPTMR)?
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IO_XIP_EN : boolean -- implement execute in place module (XIP)?
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);
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);
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port (
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port (
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-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic -- transfer error
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);
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);
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end neorv32_sysinfo;
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end neorv32_sysinfo;
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|
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architecture neorv32_sysinfo_rtl of neorv32_sysinfo is
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architecture neorv32_sysinfo_rtl of neorv32_sysinfo is
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|
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| Line 109... |
Line 112... |
constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit
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constant lo_abb_c : natural := index_size_f(sysinfo_size_c); -- low address boundary bit
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|
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-- access control --
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal acc_en : std_ulogic; -- module access enable
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signal addr : std_ulogic_vector(31 downto 0);
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signal rden : std_ulogic;
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signal rden : std_ulogic;
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signal info_addr : std_ulogic_vector(02 downto 0);
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signal wren : std_ulogic;
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signal iaddr : std_ulogic_vector(02 downto 0);
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|
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-- system information ROM --
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-- system information ROM --
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type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
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type info_mem_t is array (0 to 7) of std_ulogic_vector(31 downto 0);
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signal sysinfo_mem : info_mem_t;
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signal sysinfo_mem : info_mem_t;
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|
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begin
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begin
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|
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = sysinfo_base_c(hi_abb_c downto lo_abb_c)) else '0';
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rden <= acc_en and rden_i; -- valid read access
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rden <= acc_en and rden_i; -- read access
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addr <= sysinfo_base_c(31 downto lo_abb_c) & addr_i(lo_abb_c-1 downto 2) & "00"; -- word aligned
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wren <= acc_en and wren_i; -- write access
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info_addr <= addr(index_size_f(sysinfo_size_c)-1 downto 2);
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iaddr <= addr_i(index_size_f(sysinfo_size_c)-1 downto 2);
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|
|
|
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-- Construct Info ROM ---------------------------------------------------------------------
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-- Construct Info ROM ---------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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|
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-- SYSINFO(0): Processor (primary) clock frequency --
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-- SYSINFO(0): Processor (primary) clock frequency --
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sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
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sysinfo_mem(0) <= std_ulogic_vector(to_unsigned(CLOCK_FREQUENCY, 32));
|
|
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-- SYSINFO(1): CPU configuration --
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-- SYSINFO(1): CPU configuration --
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sysinfo_mem(1)(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
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sysinfo_mem(1)(00) <= bool_to_ulogic_f(CPU_EXTENSION_RISCV_Zicsr); -- Zicsr
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| Line 181... |
Line 183... |
sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_SLINK_EN); -- stream links (SLINK) implemented?
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sysinfo_mem(2)(25) <= bool_to_ulogic_f(IO_SLINK_EN); -- stream links (SLINK) implemented?
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sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented?
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sysinfo_mem(2)(26) <= bool_to_ulogic_f(IO_UART1_EN); -- secondary universal asynchronous receiver/transmitter (UART1) implemented?
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sysinfo_mem(2)(27) <= bool_to_ulogic_f(IO_NEOLED_EN); -- NeoPixel-compatible smart LED interface (NEOLED) implemented?
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sysinfo_mem(2)(27) <= bool_to_ulogic_f(IO_NEOLED_EN); -- NeoPixel-compatible smart LED interface (NEOLED) implemented?
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sysinfo_mem(2)(28) <= bool_to_ulogic_f(boolean(IO_XIRQ_NUM_CH > 0)); -- external interrupt controller (XIRQ) implemented?
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sysinfo_mem(2)(28) <= bool_to_ulogic_f(boolean(IO_XIRQ_NUM_CH > 0)); -- external interrupt controller (XIRQ) implemented?
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sysinfo_mem(2)(29) <= bool_to_ulogic_f(IO_GPTMR_EN); -- general purpose timer (GPTMR) implemented?
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sysinfo_mem(2)(29) <= bool_to_ulogic_f(IO_GPTMR_EN); -- general purpose timer (GPTMR) implemented?
|
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sysinfo_mem(2)(30) <= bool_to_ulogic_f(IO_XIP_EN); -- execute in place module (XIP) implemented?
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--
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--
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sysinfo_mem(2)(31 downto 30) <= (others => '0'); -- reserved
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sysinfo_mem(2)(31) <= '0'; -- reserved
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|
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-- SYSINFO(3): Cache configuration --
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-- SYSINFO(3): Cache configuration --
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sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
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sysinfo_mem(3)(03 downto 00) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_BLOCK_SIZE), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(block_size_in_bytes)
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sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(number_of_block)
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sysinfo_mem(3)(07 downto 04) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_NUM_BLOCKS), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(number_of_block)
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sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(associativity)
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sysinfo_mem(3)(11 downto 08) <= std_ulogic_vector(to_unsigned(index_size_f(ICACHE_ASSOCIATIVITY), 4)) when (ICACHE_EN = true) else (others => '0'); -- i-cache: log2(associativity)
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| Line 214... |
Line 217... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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read_access: process(clk_i)
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read_access: process(clk_i)
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begin
|
begin
|
if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= rden;
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ack_o <= rden;
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err_o <= wren;
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rden = '1') then
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if (rden = '1') then
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data_o <= sysinfo_mem(to_integer(unsigned(info_addr)));
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data_o <= sysinfo_mem(to_integer(unsigned(iaddr)));
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end if;
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end if;
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end if;
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end if;
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end process read_access;
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end process read_access;
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|
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