| Line 50... |
Line 50... |
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
CLOCK_FREQUENCY : natural := 0; -- clock frequency of clk_i in Hz
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
HART_ID : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom hardware thread ID
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
BOOTLOADER_USE : boolean := true; -- implement processor-internal bootloader?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
CSR_COUNTERS_USE : boolean := true; -- implement RISC-V perf. counters ([m]instret[h], [m]cycle[h], time[h])?
|
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_C : boolean := true; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M : boolean := true; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
|
-- Memory configuration: Instruction memory --
|
-- Memory configuration: Instruction memory --
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
|
| Line 140... |
Line 140... |
signal spi_cg_en : std_ulogic;
|
signal spi_cg_en : std_ulogic;
|
signal twi_cg_en : std_ulogic;
|
signal twi_cg_en : std_ulogic;
|
signal pwm_cg_en : std_ulogic;
|
signal pwm_cg_en : std_ulogic;
|
|
|
-- cpu bus --
|
-- cpu bus --
|
signal cpu_addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
type cpu_bus_t is record
|
signal cpu_rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
addr : std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
|
signal cpu_wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
rdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
|
signal cpu_ben : std_ulogic_vector(03 downto 0); -- byte enable
|
wdata : std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
|
signal cpu_we : std_ulogic; -- write enable
|
ben : std_ulogic_vector(03 downto 0); -- byte enable
|
signal cpu_re : std_ulogic; -- read enable
|
we : std_ulogic; -- write enable
|
signal cpu_ack : std_ulogic; -- bus transfer acknowledge
|
re : std_ulogic; -- read enable
|
signal cpu_err : std_ulogic; -- bus transfer error
|
cancel : std_ulogic; -- cancel current transfer
|
|
ack : std_ulogic; -- bus transfer acknowledge
|
|
err : std_ulogic; -- bus transfer error
|
|
end record;
|
|
signal cpu : cpu_bus_t;
|
|
|
-- io space access --
|
-- io space access --
|
signal io_acc : std_ulogic;
|
signal io_acc : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_wren : std_ulogic;
|
signal io_wren : std_ulogic;
|
| Line 196... |
Line 200... |
signal wdt_irq : std_ulogic;
|
signal wdt_irq : std_ulogic;
|
signal uart_irq : std_ulogic;
|
signal uart_irq : std_ulogic;
|
signal spi_irq : std_ulogic;
|
signal spi_irq : std_ulogic;
|
signal twi_irq : std_ulogic;
|
signal twi_irq : std_ulogic;
|
|
|
|
-- misc --
|
|
signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
|
|
|
begin
|
begin
|
|
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- Sanity Checks --------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
sanity_check: process(clk_i)
|
sanity_check: process(clk_i)
|
| Line 353... |
Line 360... |
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
-- bus interface --
|
-- bus interface --
|
bus_addr_o => cpu_addr, -- bus access address
|
bus_addr_o => cpu.addr, -- bus access address
|
bus_rdata_i => cpu_rdata, -- bus read data
|
bus_rdata_i => cpu.rdata, -- bus read data
|
bus_wdata_o => cpu_wdata, -- bus write data
|
bus_wdata_o => cpu.wdata, -- bus write data
|
bus_ben_o => cpu_ben, -- byte enable
|
bus_ben_o => cpu.ben, -- byte enable
|
bus_we_o => cpu_we, -- write enable
|
bus_we_o => cpu.we, -- write enable
|
bus_re_o => cpu_re, -- read enable
|
bus_re_o => cpu.re, -- read enable
|
bus_ack_i => cpu_ack, -- bus transfer acknowledge
|
bus_cancel_o => cpu.cancel, -- cancel current bus transaction
|
bus_err_i => cpu_err, -- bus transfer error
|
bus_ack_i => cpu.ack, -- bus transfer acknowledge
|
|
bus_err_i => cpu.err, -- bus transfer error
|
|
-- system time input from MTIME --
|
|
time_i => mtime_time, -- current system time
|
-- external interrupts --
|
-- external interrupts --
|
clic_irq_i => clic_irq, -- CLIC interrupt request
|
clic_irq_i => clic_irq, -- CLIC interrupt request
|
mtime_irq_i => mtime_irq -- machine timer interrupt
|
mtime_irq_i => mtime_irq -- machine timer interrupt
|
);
|
);
|
|
|
-- CPU data input --
|
-- CPU data input --
|
cpu_rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
|
cpu.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
|
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata);
|
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata);
|
|
|
-- CPU ACK input --
|
-- CPU ACK input --
|
cpu_ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
|
cpu.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
|
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack);
|
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack);
|
|
|
-- CPU bus error input --
|
-- CPU bus error input --
|
cpu_err <= wishbone_err;
|
cpu.err <= wishbone_err;
|
|
|
|
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_int_imem_inst_true:
|
neorv32_int_imem_inst_true:
|
| Line 391... |
Line 401... |
IMEM_AS_ROM => MEM_INT_IMEM_ROM, -- implement IMEM as read-only memory?
|
IMEM_AS_ROM => MEM_INT_IMEM_ROM, -- implement IMEM as read-only memory?
|
BOOTLOADER_USE => BOOTLOADER_USE -- implement and use bootloader?
|
BOOTLOADER_USE => BOOTLOADER_USE -- implement and use bootloader?
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => cpu_re, -- read enable
|
rden_i => cpu.re, -- read enable
|
wren_i => cpu_we, -- write enable
|
wren_i => cpu.we, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
upen_i => '1', -- update enable
|
upen_i => '1', -- update enable
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => imem_rdata, -- data out
|
data_o => imem_rdata, -- data out
|
ack_o => imem_ack -- transfer acknowledge
|
ack_o => imem_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 420... |
Line 430... |
DMEM_BASE => MEM_DSPACE_BASE, -- memory base address
|
DMEM_BASE => MEM_DSPACE_BASE, -- memory base address
|
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
|
DMEM_SIZE => MEM_INT_DMEM_SIZE -- processor-internal data memory size in bytes
|
)
|
)
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => cpu_re, -- read enable
|
rden_i => cpu.re, -- read enable
|
wren_i => cpu_we, -- write enable
|
wren_i => cpu.we, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => dmem_rdata, -- data out
|
data_o => dmem_rdata, -- data out
|
ack_o => dmem_ack -- transfer acknowledge
|
ack_o => dmem_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 444... |
Line 454... |
neorv32_boot_rom_inst_true:
|
neorv32_boot_rom_inst_true:
|
if (BOOTLOADER_USE = true) generate
|
if (BOOTLOADER_USE = true) generate
|
neorv32_boot_rom_inst: neorv32_boot_rom
|
neorv32_boot_rom_inst: neorv32_boot_rom
|
port map (
|
port map (
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => cpu_re, -- read enable
|
rden_i => cpu.re, -- read enable
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
data_o => bootrom_rdata, -- data out
|
data_o => bootrom_rdata, -- data out
|
ack_o => bootrom_ack -- transfer acknowledge
|
ack_o => bootrom_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 481... |
Line 491... |
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset line, low-active
|
rstn_i => sys_rstn, -- global reset line, low-active
|
-- host access --
|
-- host access --
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => cpu_re, -- read enable
|
rden_i => cpu.re, -- read enable
|
wren_i => cpu_we, -- write enable
|
wren_i => cpu.we, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => wishbone_rdata, -- data out
|
data_o => wishbone_rdata, -- data out
|
|
cancel_i => cpu.cancel, -- cancel current transaction
|
ack_o => wishbone_ack, -- transfer acknowledge
|
ack_o => wishbone_ack, -- transfer acknowledge
|
err_o => wishbone_err, -- transfer error
|
err_o => wishbone_err, -- transfer error
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_adr_o => wb_adr_o, -- address
|
wb_adr_o => wb_adr_o, -- address
|
wb_dat_i => wb_dat_i, -- read data
|
wb_dat_i => wb_dat_i, -- read data
|
| Line 519... |
Line 530... |
end generate;
|
end generate;
|
|
|
|
|
-- IO Access? -----------------------------------------------------------------------------
|
-- IO Access? -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
io_acc <= '1' when (cpu_addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
|
io_acc <= '1' when (cpu.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
|
io_rden <= io_acc and cpu_re;
|
io_rden <= io_acc and cpu.re;
|
io_wren <= io_acc and cpu_we;
|
io_wren <= io_acc and cpu.we;
|
|
|
|
|
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
|
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_gpio_inst_true:
|
neorv32_gpio_inst_true:
|
if (IO_GPIO_USE = true) generate
|
if (IO_GPIO_USE = true) generate
|
neorv32_gpio_inst: neorv32_gpio
|
neorv32_gpio_inst: neorv32_gpio
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => gpio_rdata, -- data out
|
data_o => gpio_rdata, -- data out
|
ack_o => gpio_ack, -- transfer acknowledge
|
ack_o => gpio_ack, -- transfer acknowledge
|
-- parallel io --
|
-- parallel io --
|
gpio_o => gpio_o,
|
gpio_o => gpio_o,
|
gpio_i => gpio_i,
|
gpio_i => gpio_i,
|
| Line 566... |
Line 577... |
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => clic_rdata, -- data out
|
data_o => clic_rdata, -- data out
|
ack_o => clic_ack, -- transfer acknowledge
|
ack_o => clic_ack, -- transfer acknowledge
|
-- cpu interrupt --
|
-- cpu interrupt --
|
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
|
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
|
-- external interrupt lines --
|
-- external interrupt lines --
|
| Line 613... |
Line 624... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => ext_rstn, -- global reset line, low-active
|
rstn_i => ext_rstn, -- global reset line, low-active
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => wdt_rdata, -- data out
|
data_o => wdt_rdata, -- data out
|
ack_o => wdt_ack, -- transfer acknowledge
|
ack_o => wdt_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => wdt_cg_en, -- enable clock generator
|
clkgen_en_o => wdt_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 646... |
Line 657... |
neorv32_mtime_inst: neorv32_mtime
|
neorv32_mtime_inst: neorv32_mtime
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => mtime_rdata, -- data out
|
data_o => mtime_rdata, -- data out
|
ack_o => mtime_ack, -- transfer acknowledge
|
ack_o => mtime_ack, -- transfer acknowledge
|
|
-- time output for CPU --
|
|
time_o => mtime_time, -- current system time
|
-- interrupt --
|
-- interrupt --
|
irq_o => mtime_irq -- interrupt request
|
irq_o => mtime_irq -- interrupt request
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_mtime_inst_false:
|
neorv32_mtime_inst_false:
|
if (IO_MTIME_USE = false) generate
|
if (IO_MTIME_USE = false) generate
|
mtime_rdata <= (others => '0');
|
mtime_rdata <= (others => '0');
|
|
mtime_time <= (others => '0');
|
mtime_ack <= '0';
|
mtime_ack <= '0';
|
mtime_irq <= '0';
|
mtime_irq <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
| Line 674... |
Line 688... |
if (IO_UART_USE = true) generate
|
if (IO_UART_USE = true) generate
|
neorv32_uart_inst: neorv32_uart
|
neorv32_uart_inst: neorv32_uart
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => uart_rdata, -- data out
|
data_o => uart_rdata, -- data out
|
ack_o => uart_ack, -- transfer acknowledge
|
ack_o => uart_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => uart_cg_en, -- enable clock generator
|
clkgen_en_o => uart_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 710... |
Line 724... |
if (IO_SPI_USE = true) generate
|
if (IO_SPI_USE = true) generate
|
neorv32_spi_inst: neorv32_spi
|
neorv32_spi_inst: neorv32_spi
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => spi_rdata, -- data out
|
data_o => spi_rdata, -- data out
|
ack_o => spi_ack, -- transfer acknowledge
|
ack_o => spi_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => spi_cg_en, -- enable clock generator
|
clkgen_en_o => spi_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 750... |
Line 764... |
if (IO_TWI_USE = true) generate
|
if (IO_TWI_USE = true) generate
|
neorv32_twi_inst: neorv32_twi
|
neorv32_twi_inst: neorv32_twi
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => twi_rdata, -- data out
|
data_o => twi_rdata, -- data out
|
ack_o => twi_ack, -- transfer acknowledge
|
ack_o => twi_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => twi_cg_en, -- enable clock generator
|
clkgen_en_o => twi_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 787... |
Line 801... |
if (IO_PWM_USE = true) generate
|
if (IO_PWM_USE = true) generate
|
neorv32_pwm_inst: neorv32_pwm
|
neorv32_pwm_inst: neorv32_pwm
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => pwm_rdata, -- data out
|
data_o => pwm_rdata, -- data out
|
ack_o => pwm_ack, -- transfer acknowledge
|
ack_o => pwm_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => pwm_cg_en, -- enable clock generator
|
clkgen_en_o => pwm_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
| Line 819... |
Line 833... |
if (IO_TRNG_USE = true) generate
|
if (IO_TRNG_USE = true) generate
|
neorv32_trng_inst: neorv32_trng
|
neorv32_trng_inst: neorv32_trng
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => trng_rdata, -- data out
|
data_o => trng_rdata, -- data out
|
ack_o => trng_ack -- transfer acknowledge
|
ack_o => trng_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 844... |
Line 858... |
if (IO_DEVNULL_USE = true) generate
|
if (IO_DEVNULL_USE = true) generate
|
neorv32_devnull_inst: neorv32_devnull
|
neorv32_devnull_inst: neorv32_devnull
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => cpu_addr, -- address
|
addr_i => cpu.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => cpu_ben, -- byte write enable
|
ben_i => cpu.ben, -- byte write enable
|
data_i => cpu_wdata, -- data in
|
data_i => cpu.wdata, -- data in
|
data_o => devnull_rdata, -- data out
|
data_o => devnull_rdata, -- data out
|
ack_o => devnull_ack -- transfer acknowledge
|
ack_o => devnull_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
|
|
