| Line 78... |
Line 78... |
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE : boolean := true; -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
| Line 108... |
Line 107... |
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
-- SPI (available if IO_SPI_USE = true) --
|
-- SPI (available if IO_SPI_USE = true) --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
spi_csn_o : out std_ulogic_vector(07 downto 0); -- SPI CS
|
-- TWI (available if IO_TWI_USE = true) --
|
-- TWI (available if IO_TWI_USE = true) --
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_sda_io : inout std_logic := 'H'; -- twi serial data line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
twi_scl_io : inout std_logic := 'H'; -- twi serial clock line
|
-- PWM (available if IO_PWM_USE = true) --
|
-- PWM (available if IO_PWM_USE = true) --
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
pwm_o : out std_ulogic_vector(03 downto 0); -- pwm channels
|
-- Interrupts (available if IO_CLIC_USE = true) --
|
-- Interrupts --
|
ext_irq_i : in std_ulogic_vector(01 downto 0) := (others => '0'); -- external interrupt request
|
msw_irq_i : in std_ulogic := '0'; -- machine software interrupt
|
ext_ack_o : out std_ulogic_vector(01 downto 0) -- external interrupt request acknowledge
|
mext_irq_i : in std_ulogic := '0' -- machine external interrupt
|
);
|
);
|
end neorv32_top;
|
end neorv32_top;
|
|
|
architecture neorv32_top_rtl of neorv32_top is
|
architecture neorv32_top_rtl of neorv32_top is
|
|
|
| Line 189... |
Line 188... |
signal twi_ack : std_ulogic;
|
signal twi_ack : std_ulogic;
|
signal pwm_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal pwm_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal pwm_ack : std_ulogic;
|
signal pwm_ack : std_ulogic;
|
signal wdt_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wdt_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wdt_ack : std_ulogic;
|
signal wdt_ack : std_ulogic;
|
signal clic_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
|
signal clic_ack : std_ulogic;
|
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_ack : std_ulogic;
|
signal trng_ack : std_ulogic;
|
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal devnull_ack : std_ulogic;
|
signal devnull_ack : std_ulogic;
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal sysinfo_ack : std_ulogic;
|
signal sysinfo_ack : std_ulogic;
|
|
|
-- IRQs --
|
-- IRQs --
|
signal mtime_irq : std_ulogic;
|
signal mtime_irq : std_ulogic;
|
signal clic_irq : std_ulogic;
|
signal fast_irq : std_ulogic_vector(3 downto 0);
|
signal clic_xirq : std_ulogic_vector(7 downto 0);
|
|
signal clic_xack : std_ulogic_vector(7 downto 0);
|
|
signal gpio_irq : std_ulogic;
|
signal gpio_irq : std_ulogic;
|
signal wdt_irq : std_ulogic;
|
signal wdt_irq : std_ulogic;
|
signal uart_irq : std_ulogic;
|
signal uart_irq : std_ulogic;
|
signal spi_irq : std_ulogic;
|
signal spi_irq : std_ulogic;
|
signal twi_irq : std_ulogic;
|
signal twi_irq : std_ulogic;
|
| Line 254... |
Line 249... |
|
|
-- CSR system not implemented --
|
-- CSR system not implemented --
|
if (CPU_EXTENSION_RISCV_Zicsr = false) then
|
if (CPU_EXTENSION_RISCV_Zicsr = false) then
|
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
|
assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
|
end if;
|
end if;
|
-- core local interrupt controller --
|
|
if (CPU_EXTENSION_RISCV_Zicsr = false) and (IO_CLIC_USE = true) then
|
|
assert false report "NEORV32 CONFIG ERROR! Core local interrupt controller (CLIC) cannot be used without >Zicsr< CPU extension." severity error;
|
|
end if;
|
|
|
|
-- memory layout notifier --
|
-- memory layout notifier --
|
if (MEM_ISPACE_BASE /= x"00000000") then
|
if (MEM_ISPACE_BASE /= x"00000000") then
|
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framwork." severity warning;
|
assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framwork." severity warning;
|
end if;
|
end if;
|
| Line 337... |
Line 328... |
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
-- Memory configuration: External memory interface --
|
-- Bus Interface --
|
MEM_EXT_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
BUS_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
| Line 368... |
Line 359... |
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => mtime_time, -- current system time
|
time_i => mtime_time, -- current system time
|
-- external interrupts --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i => '0', -- software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
clic_irq_i => clic_irq, -- CLIC interrupt request
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
mtime_irq_i => mtime_irq -- machine timer interrupt
|
mtime_irq_i => mtime_irq, -- machine timer interrupt
|
|
-- fast interrupts (custom) --
|
|
firq_i => fast_irq
|
);
|
);
|
|
|
|
-- advanced memory control --
|
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
|
|
|
-- fast interrupts --
|
|
fast_irq(0) <= wdt_irq; -- highest priority
|
|
fast_irq(1) <= gpio_irq;
|
|
fast_irq(2) <= uart_irq;
|
|
fast_irq(3) <= spi_irq or twi_irq; -- lowest priority, can be triggered by SPI or TWI
|
|
|
|
|
-- CPU Crossbar Switch --------------------------------------------------------------------
|
-- CPU Crossbar Switch --------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_busswitch_inst: neorv32_busswitch
|
neorv32_busswitch_inst: neorv32_busswitch
|
generic map (
|
generic map (
|
| Line 418... |
Line 421... |
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction
|
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_err_i => p_bus.err -- bus transfer error
|
p_bus_err_i => p_bus.err -- bus transfer error
|
);
|
);
|
|
|
-- advanced memory control --
|
-- processor bus: CPU data input --
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
|
fencei_o <= cpu_i.fence; -- indicates an executed FENCEI operation
|
|
|
|
-- process bus: CPU data input --
|
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart_rdata or
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata or sysinfo_rdata);
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or devnull_rdata or sysinfo_rdata);
|
|
|
-- process bus: CPU data ACK input --
|
-- processor bus: CPU data ACK input --
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
|
p_bus.ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or uart_ack or
|
spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack or sysinfo_ack);
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or devnull_ack or sysinfo_ack);
|
|
|
-- process bus: CPU data bus error input --
|
-- processor bus: CPU data bus error input --
|
p_bus.err <= wishbone_err;
|
p_bus.err <= wishbone_err;
|
|
|
|
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
| Line 613... |
Line 612... |
gpio_o <= (others => '0');
|
gpio_o <= (others => '0');
|
gpio_irq <= '0';
|
gpio_irq <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
-- Core-Local Interrupt Controller (CLIC) -------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_clic_inst_true:
|
|
if (IO_CLIC_USE = true) generate
|
|
neorv32_clic_inst: neorv32_clic
|
|
port map (
|
|
-- host access --
|
|
clk_i => clk_i, -- global clock line
|
|
rden_i => io_rden, -- read enable
|
|
wren_i => io_wren, -- write enable
|
|
ben_i => p_bus.ben, -- byte write enable
|
|
addr_i => p_bus.addr, -- address
|
|
data_i => p_bus.wdata, -- data in
|
|
data_o => clic_rdata, -- data out
|
|
ack_o => clic_ack, -- transfer acknowledge
|
|
-- cpu interrupt --
|
|
cpu_irq_o => clic_irq, -- trigger CPU's external IRQ
|
|
-- external interrupt lines --
|
|
ext_irq_i => clic_xirq, -- IRQ, triggering on HIGH level
|
|
ext_ack_o => clic_xack -- acknowledge
|
|
);
|
|
end generate;
|
|
|
|
-- CLIC interrupt channels and priority --
|
|
clic_xirq(0) <= wdt_irq; -- highest priority
|
|
clic_xirq(1) <= '0'; -- reserved
|
|
clic_xirq(2) <= gpio_irq;
|
|
clic_xirq(3) <= uart_irq;
|
|
clic_xirq(4) <= spi_irq;
|
|
clic_xirq(5) <= twi_irq;
|
|
clic_xirq(6) <= ext_irq_i(0);
|
|
clic_xirq(7) <= ext_irq_i(1); -- lowest priority
|
|
|
|
-- external interrupt request acknowledge --
|
|
ext_ack_o(0) <= clic_xack(6);
|
|
ext_ack_o(1) <= clic_xack(7);
|
|
|
|
neorv32_clic_inst_false:
|
|
if (IO_CLIC_USE = false) generate
|
|
clic_rdata <= (others => '0');
|
|
clic_ack <= '0';
|
|
clic_irq <= '0';
|
|
clic_xack <= (others => '0');
|
|
end generate;
|
|
|
|
|
|
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
|
-- Watch Dog Timer (WDT) ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_wdt_inst_true:
|
neorv32_wdt_inst_true:
|
if (IO_WDT_USE = true) generate
|
if (IO_WDT_USE = true) generate
|
neorv32_wdt_inst: neorv32_wdt
|
neorv32_wdt_inst: neorv32_wdt
|
| Line 950... |
Line 903... |
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_UART_USE => IO_UART_USE, -- implement universal asynchronous receiver/transmitter (UART)?
|
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
|
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
|
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
|
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
|
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
|
|
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
|
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
|
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
|
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
|
)
|
)
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
