| Line 53... |
Line 53... |
USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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USER_CODE : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_C : boolean := false; -- implement compressed extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E : boolean := false; -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M : boolean := false; -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U : boolean := false; -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr : boolean := true; -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei : boolean := true; -- implement instruction stream sync.?
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-- Physical Memory Protection (PMP) --
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PMP_USE : boolean := false; -- implement PMP?
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PMP_NUM_REGIONS : natural := 4; -- number of regions (max 16)
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PMP_GRANULARITY : natural := 15; -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Memory configuration: Instruction memory --
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-- Memory configuration: Instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_ISPACE_SIZE : natural := 16*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 16*1024; -- size of processor-internal instruction memory in bytes
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| Line 245... |
Line 250... |
-- clock --
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-- clock --
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if (CLOCK_FREQUENCY = 0) then
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if (CLOCK_FREQUENCY = 0) then
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assert false report "NEORV32 CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
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assert false report "NEORV32 CONFIG ERROR! Core clock frequency (CLOCK_FREQUENCY) not specified." severity error;
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end if;
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end if;
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|
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-- CSR system not implemented --
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if (CPU_EXTENSION_RISCV_Zicsr = false) then
|
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assert false report "NEORV32 CONFIG WARNING! No exception/interrupt/machine features available when CPU_EXTENSION_RISCV_Zicsr = false." severity warning;
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end if;
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|
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-- memory layout notifier --
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-- memory layout notifier --
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if (MEM_ISPACE_BASE /= x"00000000") then
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if (MEM_ISPACE_BASE /= x"00000000") then
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assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framwork." severity warning;
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assert false report "NEORV32 CONFIG WARNING! Non-default base address for instruction address space. Make sure this is sync with the software framwork." severity warning;
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end if;
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end if;
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if (MEM_DSPACE_BASE /= x"80000000") then
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if (MEM_DSPACE_BASE /= x"80000000") then
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| Line 326... |
Line 326... |
CPU_BOOT_ADDR => boot_addr_c, -- cpu boot address
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CPU_BOOT_ADDR => boot_addr_c, -- cpu boot address
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
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CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
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-- Physical Memory Protection (PMP) --
|
|
PMP_USE => PMP_USE, -- implement PMP?
|
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PMP_NUM_REGIONS => PMP_NUM_REGIONS, -- number of regions (max 16)
|
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PMP_GRANULARITY => PMP_GRANULARITY, -- region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
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-- Bus Interface --
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-- Bus Interface --
|
BUS_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
|
BUS_TIMEOUT => MEM_EXT_TIMEOUT -- cycles after which a valid bus access will timeout
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)
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)
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port map (
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port map (
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-- global control --
|
-- global control --
|
