| Line 107... |
Line 107... |
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
-- Advanced memory control signals (available if MEM_EXT_USE = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
fencei_o : out std_ulogic; -- indicates an executed FENCEI operation
|
-- GPIO (available if IO_GPIO_USE = true) --
|
-- GPIO (available if IO_GPIO_USE = true) --
|
gpio_o : out std_ulogic_vector(15 downto 0); -- parallel output
|
gpio_o : out std_ulogic_vector(31 downto 0); -- parallel output
|
gpio_i : in std_ulogic_vector(15 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
-- UART (available if IO_UART_USE = true) --
|
-- UART (available if IO_UART_USE = true) --
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_txd_o : out std_ulogic; -- UART send data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
uart_rxd_i : in std_ulogic := '0'; -- UART receive data
|
-- SPI (available if IO_SPI_USE = true) --
|
-- SPI (available if IO_SPI_USE = true) --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
| Line 226... |
Line 226... |
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
-- internal bootloader memory --
|
-- internal bootloader memory --
|
if (BOOTLOADER_USE = true) and (boot_size_c > boot_max_size_c) then
|
if (BOOTLOADER_USE = true) and (boot_size_c > boot_max_size_c) then
|
assert false report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range." severity error;
|
assert false report "NEORV32 PROCESSOR CONFIG ERROR! Boot ROM size out of range." severity error;
|
end if;
|
end if;
|
|
if (BOOTLOADER_USE = true) and (MEM_INT_IMEM_ROM = true) then
|
|
assert false report "NEORV32 PROCESSOR CONFIG WARNING! IMEM is configured as read-only. Bootloader will not be able to load new executables." severity warning;
|
|
end if;
|
|
|
-- memory system - data/instruction fetch --
|
-- memory system - data/instruction fetch --
|
if (MEM_EXT_USE = false) then
|
if (MEM_EXT_USE = false) then
|
if (MEM_INT_DMEM_USE = false) then
|
if (MEM_INT_DMEM_USE = false) then
|
assert false report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error;
|
assert false report "NEORV32 PROCESSOR CONFIG ERROR! Core cannot fetch data without external memory interface and internal data memory." severity error;
|
| Line 593... |
Line 596... |
|
|
-- IO Access? -----------------------------------------------------------------------------
|
-- IO Access? -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
|
io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
|
io_rden <= io_acc and p_bus.re;
|
io_rden <= io_acc and p_bus.re;
|
io_wren <= io_acc and p_bus.we;
|
-- the peripheral/IO devices in the IO area can only be written in word mode (reduces HW complexity)
|
|
io_wren <= io_acc and p_bus.we and p_bus.ben(3) and p_bus.ben(2) and p_bus.ben(1) and p_bus.ben(0);
|
|
|
|
|
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
|
-- General Purpose Input/Output Port (GPIO) -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_gpio_inst_true:
|
neorv32_gpio_inst_true:
|
| Line 607... |
Line 611... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => gpio_rdata, -- data out
|
data_o => gpio_rdata, -- data out
|
ack_o => gpio_ack, -- transfer acknowledge
|
ack_o => gpio_ack, -- transfer acknowledge
|
-- parallel io --
|
-- parallel io --
|
gpio_o => gpio_o,
|
gpio_o => gpio_o,
|
| Line 639... |
Line 642... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => ext_rstn, -- global reset line, low-active
|
rstn_i => ext_rstn, -- global reset line, low-active
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => wdt_rdata, -- data out
|
data_o => wdt_rdata, -- data out
|
ack_o => wdt_ack, -- transfer acknowledge
|
ack_o => wdt_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
| Line 675... |
Line 677... |
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => mtime_rdata, -- data out
|
data_o => mtime_rdata, -- data out
|
ack_o => mtime_ack, -- transfer acknowledge
|
ack_o => mtime_ack, -- transfer acknowledge
|
-- time output for CPU --
|
-- time output for CPU --
|
time_o => mtime_time, -- current system time
|
time_o => mtime_time, -- current system time
|
| Line 706... |
Line 707... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => uart_rdata, -- data out
|
data_o => uart_rdata, -- data out
|
ack_o => uart_ack, -- transfer acknowledge
|
ack_o => uart_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => uart_cg_en, -- enable clock generator
|
clkgen_en_o => uart_cg_en, -- enable clock generator
|
| Line 742... |
Line 742... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => spi_rdata, -- data out
|
data_o => spi_rdata, -- data out
|
ack_o => spi_ack, -- transfer acknowledge
|
ack_o => spi_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => spi_cg_en, -- enable clock generator
|
clkgen_en_o => spi_cg_en, -- enable clock generator
|
| Line 782... |
Line 781... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => twi_rdata, -- data out
|
data_o => twi_rdata, -- data out
|
ack_o => twi_ack, -- transfer acknowledge
|
ack_o => twi_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => twi_cg_en, -- enable clock generator
|
clkgen_en_o => twi_cg_en, -- enable clock generator
|
| Line 819... |
Line 817... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => pwm_rdata, -- data out
|
data_o => pwm_rdata, -- data out
|
ack_o => pwm_ack, -- transfer acknowledge
|
ack_o => pwm_ack, -- transfer acknowledge
|
-- clock generator --
|
-- clock generator --
|
clkgen_en_o => pwm_cg_en, -- enable clock generator
|
clkgen_en_o => pwm_cg_en, -- enable clock generator
|
| Line 851... |
Line 848... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => trng_rdata, -- data out
|
data_o => trng_rdata, -- data out
|
ack_o => trng_ack -- transfer acknowledge
|
ack_o => trng_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
| Line 876... |
Line 872... |
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
|
addr_i => p_bus.addr, -- address
|
addr_i => p_bus.addr, -- address
|
rden_i => io_rden, -- read enable
|
rden_i => io_rden, -- read enable
|
wren_i => io_wren, -- write enable
|
wren_i => io_wren, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => devnull_rdata, -- data out
|
data_o => devnull_rdata, -- data out
|
ack_o => devnull_ack -- transfer acknowledge
|
ack_o => devnull_ack -- transfer acknowledge
|
);
|
);
|
end generate;
|
end generate;
|
