| Line 77... |
Line 77... |
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_USE : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE : boolean := true; -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_USE : boolean := true; -- implement watch dog timer (WDT)?
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
IO_CLIC_USE : boolean := true; -- implement core local interrupt controller (CLIC)?
|
IO_TRNG_USE : boolean := false -- implement true random number generator (TRNG)?
|
IO_TRNG_USE : boolean := false; -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE : boolean := true -- implement dummy device (DEVNULL)?
|
);
|
);
|
port (
|
port (
|
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
| Line 179... |
Line 180... |
signal wdt_ack : std_ulogic;
|
signal wdt_ack : std_ulogic;
|
signal clic_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal clic_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal clic_ack : std_ulogic;
|
signal clic_ack : std_ulogic;
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal trng_ack : std_ulogic;
|
signal trng_ack : std_ulogic;
|
|
signal devnull_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
|
signal devnull_ack : std_ulogic;
|
|
|
-- IRQs --
|
-- IRQs --
|
signal mtime_irq : std_ulogic;
|
signal mtime_irq : std_ulogic;
|
signal clic_irq : std_ulogic;
|
signal clic_irq : std_ulogic;
|
signal clic_xirq : std_ulogic_vector(7 downto 0);
|
signal clic_xirq : std_ulogic_vector(7 downto 0);
|
| Line 338... |
Line 341... |
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
|
IO_SPI_USE => IO_SPI_USE, -- implement serial peripheral interface (SPI)?
|
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
|
IO_TWI_USE => IO_TWI_USE, -- implement two-wire interface (TWI)?
|
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
|
IO_PWM_USE => IO_PWM_USE, -- implement pulse-width modulation unit (PWM)?
|
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
|
IO_WDT_USE => IO_WDT_USE, -- implement watch dog timer (WDT)?
|
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
|
IO_CLIC_USE => IO_CLIC_USE, -- implement core local interrupt controller (CLIC)?
|
IO_TRNG_USE => IO_TRNG_USE -- implement true random number generator (TRNG)?
|
IO_TRNG_USE => IO_TRNG_USE, -- implement true random number generator (TRNG)?
|
|
IO_DEVNULL_USE => IO_DEVNULL_USE -- implement dummy device (DEVNULL)?
|
)
|
)
|
port map (
|
port map (
|
-- global control --
|
-- global control --
|
clk_i => clk_i, -- global clock, rising edge
|
clk_i => clk_i, -- global clock, rising edge
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
rstn_i => sys_rstn, -- global reset, low-active, async
|
| Line 360... |
Line 364... |
mtime_irq_i => mtime_irq -- machine timer interrupt
|
mtime_irq_i => mtime_irq -- machine timer interrupt
|
);
|
);
|
|
|
-- CPU data input --
|
-- CPU data input --
|
cpu_rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
|
cpu_rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or
|
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata);
|
uart_rdata or spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or clic_rdata or trng_rdata or devnull_rdata);
|
|
|
-- CPU ACK input --
|
-- CPU ACK input --
|
cpu_ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
|
cpu_ack <= (imem_ack or dmem_ack or bootrom_ack) or wishbone_ack or (gpio_ack or mtime_ack or
|
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack);
|
uart_ack or spi_ack or twi_ack or pwm_ack or wdt_ack or clic_ack or trng_ack or devnull_ack);
|
|
|
-- CPU bus error input --
|
-- CPU bus error input --
|
cpu_err <= wishbone_err;
|
cpu_err <= wishbone_err;
|
|
|
|
|
| Line 825... |
Line 829... |
trng_rdata <= (others => '0');
|
trng_rdata <= (others => '0');
|
trng_ack <= '0';
|
trng_ack <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
|
-- Dummy Device (DEVNULL) -----------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
neorv32_devnull_inst_true:
|
|
if (IO_DEVNULL_USE = true) generate
|
|
neorv32_devnull_inst: neorv32_devnull
|
|
port map (
|
|
-- host access --
|
|
clk_i => clk_i, -- global clock line
|
|
addr_i => cpu_addr, -- address
|
|
rden_i => io_rden, -- read enable
|
|
wren_i => io_wren, -- write enable
|
|
ben_i => cpu_ben, -- byte write enable
|
|
data_i => cpu_wdata, -- data in
|
|
data_o => devnull_rdata, -- data out
|
|
ack_o => devnull_ack -- transfer acknowledge
|
|
);
|
|
end generate;
|
|
|
|
neorv32_devnull_inst_false:
|
|
if (IO_DEVNULL_USE = false) generate
|
|
devnull_rdata <= (others => '0');
|
|
devnull_ack <= '0';
|
|
end generate;
|
|
|
|
|
end neorv32_top_rtl;
|
end neorv32_top_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
