URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_top.vhd] - Diff between revs 30 and 31

Rev 30	Rev 31
Line 509...	Line 509...
`neorv32_wishbone_inst_true:`	`neorv32_wishbone_inst_true:`
`if (MEM_EXT_USE = true) generate`	`if (MEM_EXT_USE = true) generate`
`neorv32_wishbone_inst: neorv32_wishbone`	`neorv32_wishbone_inst: neorv32_wishbone`
`generic map (`	`generic map (`
`INTERFACE_REG_STAGES => MEM_EXT_REG_STAGES, -- number of interface register stages (0,1,2)`	`INTERFACE_REG_STAGES => MEM_EXT_REG_STAGES, -- number of interface register stages (0,1,2)`
	`WB_PIPELINED_MODE => wb_pipe_mode_c, -- false: classic/standard wishbone mode, true: pipelined wishbone mode`
`-- Internal instruction memory --`	`-- Internal instruction memory --`
`MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory`	`MEM_INT_IMEM_USE => MEM_INT_IMEM_USE, -- implement processor-internal instruction memory`
`MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes`	`MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE, -- size of processor-internal instruction memory in bytes`
`-- Internal data memory --`	`-- Internal data memory --`
`MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory`	`MEM_INT_DMEM_USE => MEM_INT_DMEM_USE, -- implement processor-internal data memory`