| Line 133... |
Line 133... |
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
gpio_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
|
|
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
-- primary UART0 (available if IO_UART0_EN = true) --
|
uart0_txd_o : out std_ulogic; -- UART0 send data
|
uart0_txd_o : out std_ulogic; -- UART0 send data
|
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
|
uart0_rxd_i : in std_ulogic := '0'; -- UART0 receive data
|
|
uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
|
|
uart0_cts_i : in std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
|
|
|
-- secondary UART1 (available if IO_UART1_EN = true) --
|
-- secondary UART1 (available if IO_UART1_EN = true) --
|
uart1_txd_o : out std_ulogic; -- UART1 send data
|
uart1_txd_o : out std_ulogic; -- UART1 send data
|
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
|
uart1_rxd_i : in std_ulogic := '0'; -- UART1 receive data
|
|
uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
|
|
uart1_cts_i : in std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
|
|
|
-- SPI (available if IO_SPI_EN = true) --
|
-- SPI (available if IO_SPI_EN = true) --
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sck_o : out std_ulogic; -- SPI serial clock
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdo_o : out std_ulogic; -- controller data out, peripheral data in
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
spi_sdi_i : in std_ulogic := '0'; -- controller data in, peripheral data out
|
| Line 477... |
Line 481... |
fast_irq(12) <= soc_firq_i(2);
|
fast_irq(12) <= soc_firq_i(2);
|
fast_irq(13) <= soc_firq_i(3);
|
fast_irq(13) <= soc_firq_i(3);
|
fast_irq(14) <= soc_firq_i(4);
|
fast_irq(14) <= soc_firq_i(4);
|
fast_irq(15) <= soc_firq_i(5);
|
fast_irq(15) <= soc_firq_i(5);
|
|
|
-- IRQ acknowledge --
|
-- CFS IRQ acknowledge --
|
cfs_irq_ack <= fast_irq_ack(2);
|
cfs_irq_ack <= fast_irq_ack(1);
|
|
|
|
|
-- CPU Instruction Cache ------------------------------------------------------------------
|
-- CPU Instruction Cache ------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_icache_inst_true:
|
neorv32_icache_inst_true:
|
| Line 890... |
Line 894... |
mtime_ack <= '0';
|
mtime_ack <= '0';
|
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
mtime_irq <= mtime_irq_i; -- use external machine timer interrupt
|
end generate;
|
end generate;
|
|
|
|
|
-- Universal Asynchronous Receiver/Transmitter 0, Primary UART (UART0) --------------------
|
-- Primary Universal Asynchronous Receiver/Transmitter (UART0) ----------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_uart0_inst_true:
|
neorv32_uart0_inst_true:
|
if (IO_UART0_EN = true) generate
|
if (IO_UART0_EN = true) generate
|
neorv32_uart0_inst: neorv32_uart
|
neorv32_uart0_inst: neorv32_uart
|
generic map (
|
generic map (
|
| Line 913... |
Line 917... |
clkgen_en_o => uart0_cg_en, -- enable clock generator
|
clkgen_en_o => uart0_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
-- com lines --
|
-- com lines --
|
uart_txd_o => uart0_txd_o,
|
uart_txd_o => uart0_txd_o,
|
uart_rxd_i => uart0_rxd_i,
|
uart_rxd_i => uart0_rxd_i,
|
|
-- hardware flow control --
|
|
uart_rts_o => uart0_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
|
|
uart_cts_i => uart0_cts_i, -- UART.TX allowed to transmit, low-active, optional
|
-- interrupts --
|
-- interrupts --
|
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
|
irq_rxd_o => uart0_rxd_irq, -- uart data received interrupt
|
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
|
irq_txd_o => uart0_txd_irq -- uart transmission done interrupt
|
);
|
);
|
end generate;
|
end generate;
|
| Line 924... |
Line 931... |
neorv32_uart0_inst_false:
|
neorv32_uart0_inst_false:
|
if (IO_UART0_EN = false) generate
|
if (IO_UART0_EN = false) generate
|
uart0_rdata <= (others => '0');
|
uart0_rdata <= (others => '0');
|
uart0_ack <= '0';
|
uart0_ack <= '0';
|
uart0_txd_o <= '0';
|
uart0_txd_o <= '0';
|
|
uart0_rts_o <= '0';
|
uart0_cg_en <= '0';
|
uart0_cg_en <= '0';
|
uart0_rxd_irq <= '0';
|
uart0_rxd_irq <= '0';
|
uart0_txd_irq <= '0';
|
uart0_txd_irq <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
-- Universal Asynchronous Receiver/Transmitter 1, Secondary UART (UART1) ------------------
|
-- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_uart1_inst_true:
|
neorv32_uart1_inst_true:
|
if (IO_UART1_EN = true) generate
|
if (IO_UART1_EN = true) generate
|
neorv32_uart1_inst: neorv32_uart
|
neorv32_uart1_inst: neorv32_uart
|
generic map (
|
generic map (
|
| Line 953... |
Line 961... |
clkgen_en_o => uart1_cg_en, -- enable clock generator
|
clkgen_en_o => uart1_cg_en, -- enable clock generator
|
clkgen_i => clk_gen,
|
clkgen_i => clk_gen,
|
-- com lines --
|
-- com lines --
|
uart_txd_o => uart1_txd_o,
|
uart_txd_o => uart1_txd_o,
|
uart_rxd_i => uart1_rxd_i,
|
uart_rxd_i => uart1_rxd_i,
|
|
-- hardware flow control --
|
|
uart_rts_o => uart1_rts_o, -- UART.RX ready to receive ("RTR"), low-active, optional
|
|
uart_cts_i => uart1_cts_i, -- UART.TX allowed to transmit, low-active, optional
|
-- interrupts --
|
-- interrupts --
|
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
|
irq_rxd_o => uart1_rxd_irq, -- uart data received interrupt
|
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
|
irq_txd_o => uart1_txd_irq -- uart transmission done interrupt
|
);
|
);
|
end generate;
|
end generate;
|
| Line 964... |
Line 975... |
neorv32_uart1_inst_false:
|
neorv32_uart1_inst_false:
|
if (IO_UART1_EN = false) generate
|
if (IO_UART1_EN = false) generate
|
uart1_rdata <= (others => '0');
|
uart1_rdata <= (others => '0');
|
uart1_ack <= '0';
|
uart1_ack <= '0';
|
uart1_txd_o <= '0';
|
uart1_txd_o <= '0';
|
|
uart1_rts_o <= '0';
|
uart1_cg_en <= '0';
|
uart1_cg_en <= '0';
|
uart1_rxd_irq <= '0';
|
uart1_rxd_irq <= '0';
|
uart1_txd_irq <= '0';
|
uart1_txd_irq <= '0';
|
end generate;
|
end generate;
|
|
|
| Line 1038... |
Line 1050... |
|
|
neorv32_twi_inst_false:
|
neorv32_twi_inst_false:
|
if (IO_TWI_EN = false) generate
|
if (IO_TWI_EN = false) generate
|
twi_rdata <= (others => '0');
|
twi_rdata <= (others => '0');
|
twi_ack <= '0';
|
twi_ack <= '0';
|
-- twi_sda_io <= 'Z';
|
-- twi_sda_io <= 'Z'; -- FIXME?
|
-- twi_scl_io <= 'Z';
|
-- twi_scl_io <= 'Z'; -- FIXME?
|
twi_cg_en <= '0';
|
twi_cg_en <= '0';
|
twi_irq <= '0';
|
twi_irq <= '0';
|
end generate;
|
end generate;
|
|
|
|
|
