| Line 113... |
Line 113... |
-- Global control --
|
-- Global control --
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
clk_i : in std_ulogic := '0'; -- global clock, rising edge
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
rstn_i : in std_ulogic := '0'; -- global reset, low-active, async
|
|
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
-- Wishbone bus interface (available if MEM_EXT_EN = true) --
|
wb_tag_o : out std_ulogic_vector(02 downto 0); -- tag
|
wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_i : in std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
|
wb_we_o : out std_ulogic; -- read/write
|
wb_we_o : out std_ulogic; -- read/write
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_stb_o : out std_ulogic; -- strobe
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_cyc_o : out std_ulogic; -- valid cycle
|
wb_lock_o : out std_ulogic; -- locked/exclusive bus access
|
wb_tag_i : in std_ulogic := '0'; -- response tag
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_ack_i : in std_ulogic := '0'; -- transfer acknowledge
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
wb_err_i : in std_ulogic := '0'; -- transfer error
|
|
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
fence_o : out std_ulogic; -- indicates an executed FENCE operation
|
| Line 231... |
Line 231... |
ack : std_ulogic; -- bus transfer acknowledge
|
ack : std_ulogic; -- bus transfer acknowledge
|
err : std_ulogic; -- bus transfer error
|
err : std_ulogic; -- bus transfer error
|
fence : std_ulogic; -- fence(i) instruction executed
|
fence : std_ulogic; -- fence(i) instruction executed
|
priv : std_ulogic_vector(1 downto 0); -- current privilege level
|
priv : std_ulogic_vector(1 downto 0); -- current privilege level
|
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
src : std_ulogic; -- access source (1=instruction fetch, 0=data access)
|
lock : std_ulogic; -- locked/exclusive (=atomic) access
|
excl : std_ulogic; -- exclusive access
|
end record;
|
end record;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
signal cpu_i, i_cache, cpu_d, p_bus : bus_interface_t;
|
|
signal cpu_d_exclr : std_ulogic; -- CPU D-bus, exclusive access response
|
|
|
-- io space access --
|
-- io space access --
|
signal io_acc : std_ulogic;
|
signal io_acc : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_rden : std_ulogic;
|
signal io_wren : std_ulogic;
|
signal io_wren : std_ulogic;
|
| Line 250... |
Line 251... |
signal bootrom_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal bootrom_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal bootrom_ack : std_ulogic;
|
signal bootrom_ack : std_ulogic;
|
signal wishbone_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wishbone_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal wishbone_ack : std_ulogic;
|
signal wishbone_ack : std_ulogic;
|
signal wishbone_err : std_ulogic;
|
signal wishbone_err : std_ulogic;
|
|
signal wishbone_exclr : std_ulogic;
|
signal gpio_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal gpio_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal gpio_ack : std_ulogic;
|
signal gpio_ack : std_ulogic;
|
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mtime_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal mtime_ack : std_ulogic;
|
signal mtime_ack : std_ulogic;
|
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
signal uart0_rdata : std_ulogic_vector(data_width_c-1 downto 0);
|
| Line 409... |
Line 411... |
-- RISC-V CPU Extensions --
|
-- RISC-V CPU Extensions --
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_A => CPU_EXTENSION_RISCV_A, -- implement atomic extension?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_B => CPU_EXTENSION_RISCV_B, -- implement bit manipulation extensions?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_C => CPU_EXTENSION_RISCV_C, -- implement compressed extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_E => CPU_EXTENSION_RISCV_E, -- implement embedded RF extension?
|
CPU_EXTENSION_RISCV_F => false, -- implement 32-bit floating-point extension?
|
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_M => CPU_EXTENSION_RISCV_M, -- implement muld/div extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
CPU_EXTENSION_RISCV_U => CPU_EXTENSION_RISCV_U, -- implement user mode extension?
|
|
CPU_EXTENSION_RISCV_Zfinx => false, -- implement 32-bit floating-point extension (using INT reg!)
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zicsr => CPU_EXTENSION_RISCV_Zicsr, -- implement CSR system?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
CPU_EXTENSION_RISCV_Zifencei => CPU_EXTENSION_RISCV_Zifencei, -- implement instruction stream sync.?
|
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => FAST_MUL_EN, -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => FAST_SHIFT_EN, -- use barrel shifter for shift operations
|
| Line 440... |
Line 442... |
i_bus_cancel_o => cpu_i.cancel, -- cancel current bus transaction
|
i_bus_cancel_o => cpu_i.cancel, -- cancel current bus transaction
|
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge
|
i_bus_ack_i => cpu_i.ack, -- bus transfer acknowledge
|
i_bus_err_i => cpu_i.err, -- bus transfer error
|
i_bus_err_i => cpu_i.err, -- bus transfer error
|
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation
|
i_bus_fence_o => cpu_i.fence, -- executed FENCEI operation
|
i_bus_priv_o => cpu_i.priv, -- privilege level
|
i_bus_priv_o => cpu_i.priv, -- privilege level
|
i_bus_lock_o => cpu_i.lock, -- locked/exclusive access
|
|
-- data bus interface --
|
-- data bus interface --
|
d_bus_addr_o => cpu_d.addr, -- bus access address
|
d_bus_addr_o => cpu_d.addr, -- bus access address
|
d_bus_rdata_i => cpu_d.rdata, -- bus read data
|
d_bus_rdata_i => cpu_d.rdata, -- bus read data
|
d_bus_wdata_o => cpu_d.wdata, -- bus write data
|
d_bus_wdata_o => cpu_d.wdata, -- bus write data
|
d_bus_ben_o => cpu_d.ben, -- byte enable
|
d_bus_ben_o => cpu_d.ben, -- byte enable
|
| Line 453... |
Line 454... |
d_bus_cancel_o => cpu_d.cancel, -- cancel current bus transaction
|
d_bus_cancel_o => cpu_d.cancel, -- cancel current bus transaction
|
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
d_bus_ack_i => cpu_d.ack, -- bus transfer acknowledge
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
d_bus_err_i => cpu_d.err, -- bus transfer error
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
d_bus_fence_o => cpu_d.fence, -- executed FENCE operation
|
d_bus_priv_o => cpu_d.priv, -- privilege level
|
d_bus_priv_o => cpu_d.priv, -- privilege level
|
d_bus_lock_o => cpu_d.lock, -- locked/exclusive access
|
d_bus_excl_o => cpu_d.excl, -- exclusive access
|
|
d_bus_excl_i => cpu_d_exclr, -- state of exclusiv access (set if success)
|
-- system time input from MTIME --
|
-- system time input from MTIME --
|
time_i => mtime_time, -- current system time
|
time_i => mtime_time, -- current system time
|
-- interrupts (risc-v compliant) --
|
-- interrupts (risc-v compliant) --
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
msw_irq_i => msw_irq_i, -- machine software interrupt
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
mext_irq_i => mext_irq_i, -- machine external interrupt request
|
| Line 466... |
Line 468... |
firq_i => fast_irq, -- fast interrupt trigger
|
firq_i => fast_irq, -- fast interrupt trigger
|
firq_ack_o => fast_irq_ack -- fast interrupt acknowledge mask
|
firq_ack_o => fast_irq_ack -- fast interrupt acknowledge mask
|
);
|
);
|
|
|
-- misc --
|
-- misc --
|
|
cpu_i.excl <= '0'; -- i-fetch cannot do exclusive accesses
|
cpu_i.src <= '1'; -- initialized but unused
|
cpu_i.src <= '1'; -- initialized but unused
|
cpu_d.src <= '0'; -- initialized but unused
|
cpu_d.src <= '0'; -- initialized but unused
|
|
|
-- advanced memory control --
|
-- advanced memory control --
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
fence_o <= cpu_d.fence; -- indicates an executed FENCE operation
|
| Line 520... |
Line 523... |
host_wdata_i => cpu_i.wdata, -- bus write data
|
host_wdata_i => cpu_i.wdata, -- bus write data
|
host_ben_i => cpu_i.ben, -- byte enable
|
host_ben_i => cpu_i.ben, -- byte enable
|
host_we_i => cpu_i.we, -- write enable
|
host_we_i => cpu_i.we, -- write enable
|
host_re_i => cpu_i.re, -- read enable
|
host_re_i => cpu_i.re, -- read enable
|
host_cancel_i => cpu_i.cancel, -- cancel current bus transaction
|
host_cancel_i => cpu_i.cancel, -- cancel current bus transaction
|
host_lock_i => cpu_i.lock, -- locked/exclusive access
|
|
host_ack_o => cpu_i.ack, -- bus transfer acknowledge
|
host_ack_o => cpu_i.ack, -- bus transfer acknowledge
|
host_err_o => cpu_i.err, -- bus transfer error
|
host_err_o => cpu_i.err, -- bus transfer error
|
-- peripheral bus interface --
|
-- peripheral bus interface --
|
bus_addr_o => i_cache.addr, -- bus access address
|
bus_addr_o => i_cache.addr, -- bus access address
|
bus_rdata_i => i_cache.rdata, -- bus read data
|
bus_rdata_i => i_cache.rdata, -- bus read data
|
bus_wdata_o => i_cache.wdata, -- bus write data
|
bus_wdata_o => i_cache.wdata, -- bus write data
|
bus_ben_o => i_cache.ben, -- byte enable
|
bus_ben_o => i_cache.ben, -- byte enable
|
bus_we_o => i_cache.we, -- write enable
|
bus_we_o => i_cache.we, -- write enable
|
bus_re_o => i_cache.re, -- read enable
|
bus_re_o => i_cache.re, -- read enable
|
bus_cancel_o => i_cache.cancel, -- cancel current bus transaction
|
bus_cancel_o => i_cache.cancel, -- cancel current bus transaction
|
bus_lock_o => i_cache.lock, -- locked/exclusive access
|
|
bus_ack_i => i_cache.ack, -- bus transfer acknowledge
|
bus_ack_i => i_cache.ack, -- bus transfer acknowledge
|
bus_err_i => i_cache.err -- bus transfer error
|
bus_err_i => i_cache.err -- bus transfer error
|
);
|
);
|
end generate;
|
end generate;
|
|
|
| Line 546... |
Line 547... |
i_cache.wdata <= cpu_i.wdata;
|
i_cache.wdata <= cpu_i.wdata;
|
i_cache.ben <= cpu_i.ben;
|
i_cache.ben <= cpu_i.ben;
|
i_cache.we <= cpu_i.we;
|
i_cache.we <= cpu_i.we;
|
i_cache.re <= cpu_i.re;
|
i_cache.re <= cpu_i.re;
|
i_cache.cancel <= cpu_i.cancel;
|
i_cache.cancel <= cpu_i.cancel;
|
i_cache.lock <= cpu_i.lock;
|
|
cpu_i.ack <= i_cache.ack;
|
cpu_i.ack <= i_cache.ack;
|
cpu_i.err <= i_cache.err;
|
cpu_i.err <= i_cache.err;
|
end generate;
|
end generate;
|
|
|
|
-- no exclusive accesses for i-fetch --
|
|
i_cache.excl <= '0';
|
|
|
|
|
-- CPU Bus Switch -------------------------------------------------------------------------
|
-- CPU Bus Switch -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_busswitch_inst: neorv32_busswitch
|
neorv32_busswitch_inst: neorv32_busswitch
|
generic map (
|
generic map (
|
| Line 571... |
Line 574... |
ca_bus_wdata_i => cpu_d.wdata, -- bus write data
|
ca_bus_wdata_i => cpu_d.wdata, -- bus write data
|
ca_bus_ben_i => cpu_d.ben, -- byte enable
|
ca_bus_ben_i => cpu_d.ben, -- byte enable
|
ca_bus_we_i => cpu_d.we, -- write enable
|
ca_bus_we_i => cpu_d.we, -- write enable
|
ca_bus_re_i => cpu_d.re, -- read enable
|
ca_bus_re_i => cpu_d.re, -- read enable
|
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction
|
ca_bus_cancel_i => cpu_d.cancel, -- cancel current bus transaction
|
ca_bus_lock_i => cpu_d.lock, -- locked/exclusive access
|
ca_bus_excl_i => cpu_d.excl, -- exclusive access
|
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge
|
ca_bus_ack_o => cpu_d.ack, -- bus transfer acknowledge
|
ca_bus_err_o => cpu_d.err, -- bus transfer error
|
ca_bus_err_o => cpu_d.err, -- bus transfer error
|
-- controller interface b --
|
-- controller interface b --
|
cb_bus_addr_i => i_cache.addr, -- bus access address
|
cb_bus_addr_i => i_cache.addr, -- bus access address
|
cb_bus_rdata_o => i_cache.rdata, -- bus read data
|
cb_bus_rdata_o => i_cache.rdata, -- bus read data
|
cb_bus_wdata_i => i_cache.wdata, -- bus write data
|
cb_bus_wdata_i => i_cache.wdata, -- bus write data
|
cb_bus_ben_i => i_cache.ben, -- byte enable
|
cb_bus_ben_i => i_cache.ben, -- byte enable
|
cb_bus_we_i => i_cache.we, -- write enable
|
cb_bus_we_i => i_cache.we, -- write enable
|
cb_bus_re_i => i_cache.re, -- read enable
|
cb_bus_re_i => i_cache.re, -- read enable
|
cb_bus_cancel_i => i_cache.cancel, -- cancel current bus transaction
|
cb_bus_cancel_i => i_cache.cancel, -- cancel current bus transaction
|
cb_bus_lock_i => i_cache.lock, -- locked/exclusive access
|
cb_bus_excl_i => i_cache.excl, -- exclusive access
|
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge
|
cb_bus_ack_o => i_cache.ack, -- bus transfer acknowledge
|
cb_bus_err_o => i_cache.err, -- bus transfer error
|
cb_bus_err_o => i_cache.err, -- bus transfer error
|
-- peripheral bus --
|
-- peripheral bus --
|
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions)
|
p_bus_src_o => p_bus.src, -- access source: 0 = A (data), 1 = B (instructions)
|
p_bus_addr_o => p_bus.addr, -- bus access address
|
p_bus_addr_o => p_bus.addr, -- bus access address
|
| Line 594... |
Line 597... |
p_bus_wdata_o => p_bus.wdata, -- bus write data
|
p_bus_wdata_o => p_bus.wdata, -- bus write data
|
p_bus_ben_o => p_bus.ben, -- byte enable
|
p_bus_ben_o => p_bus.ben, -- byte enable
|
p_bus_we_o => p_bus.we, -- write enable
|
p_bus_we_o => p_bus.we, -- write enable
|
p_bus_re_o => p_bus.re, -- read enable
|
p_bus_re_o => p_bus.re, -- read enable
|
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction
|
p_bus_cancel_o => p_bus.cancel, -- cancel current bus transaction
|
p_bus_lock_o => p_bus.lock, -- locked/exclusive access
|
p_bus_excl_o => p_bus.excl, -- exclusive access
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_ack_i => p_bus.ack, -- bus transfer acknowledge
|
p_bus_err_i => p_bus.err -- bus transfer error
|
p_bus_err_i => p_bus.err -- bus transfer error
|
);
|
);
|
|
|
|
-- static signals --
|
|
p_bus.priv <= cpu_i.priv; -- current CPU privilege level: cpu_i.priv == cpu_d.priv
|
|
|
-- processor bus: CPU transfer data input --
|
-- processor bus: CPU transfer data input --
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or
|
p_bus.rdata <= (imem_rdata or dmem_rdata or bootrom_rdata) or wishbone_rdata or (gpio_rdata or mtime_rdata or uart0_rdata or uart1_rdata or
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or neoled_rdata or sysinfo_rdata);
|
spi_rdata or twi_rdata or pwm_rdata or wdt_rdata or trng_rdata or cfs_rdata or nco_rdata or neoled_rdata or sysinfo_rdata);
|
|
|
-- processor bus: CPU transfer ACK input --
|
-- processor bus: CPU transfer ACK input --
|
| Line 610... |
Line 616... |
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or neoled_ack or sysinfo_ack);
|
spi_ack or twi_ack or pwm_ack or wdt_ack or trng_ack or cfs_ack or nco_ack or neoled_ack or sysinfo_ack);
|
|
|
-- processor bus: CPU transfer data bus error input --
|
-- processor bus: CPU transfer data bus error input --
|
p_bus.err <= wishbone_err;
|
p_bus.err <= wishbone_err;
|
|
|
-- current CPU privilege level --
|
-- exclusive access status --
|
p_bus.priv <= cpu_i.priv; -- cpu_i.priv == cpu_d.priv
|
-- since all internal modules/memories are only accessible to this CPU internal atomic access cannot fail
|
|
cpu_d_exclr <= wishbone_exclr; -- only external atomic memory accesses can fail
|
|
|
|
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- Processor-Internal Instruction Memory (IMEM) -------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_int_imem_inst_true:
|
neorv32_int_imem_inst_true:
|
| Line 724... |
Line 731... |
wren_i => p_bus.we, -- write enable
|
wren_i => p_bus.we, -- write enable
|
ben_i => p_bus.ben, -- byte write enable
|
ben_i => p_bus.ben, -- byte write enable
|
data_i => p_bus.wdata, -- data in
|
data_i => p_bus.wdata, -- data in
|
data_o => wishbone_rdata, -- data out
|
data_o => wishbone_rdata, -- data out
|
cancel_i => p_bus.cancel, -- cancel current transaction
|
cancel_i => p_bus.cancel, -- cancel current transaction
|
lock_i => p_bus.lock, -- locked/exclusive bus access
|
excl_i => p_bus.excl, -- exclusive access request
|
|
excl_o => wishbone_exclr, -- state of exclusiv access (set if success)
|
ack_o => wishbone_ack, -- transfer acknowledge
|
ack_o => wishbone_ack, -- transfer acknowledge
|
err_o => wishbone_err, -- transfer error
|
err_o => wishbone_err, -- transfer error
|
priv_i => p_bus.priv, -- current CPU privilege level
|
priv_i => p_bus.priv, -- current CPU privilege level
|
-- wishbone interface --
|
-- wishbone interface --
|
wb_tag_o => wb_tag_o, -- tag
|
wb_tag_o => wb_tag_o, -- request tag
|
wb_adr_o => wb_adr_o, -- address
|
wb_adr_o => wb_adr_o, -- address
|
wb_dat_i => wb_dat_i, -- read data
|
wb_dat_i => wb_dat_i, -- read data
|
wb_dat_o => wb_dat_o, -- write data
|
wb_dat_o => wb_dat_o, -- write data
|
wb_we_o => wb_we_o, -- read/write
|
wb_we_o => wb_we_o, -- read/write
|
wb_sel_o => wb_sel_o, -- byte enable
|
wb_sel_o => wb_sel_o, -- byte enable
|
wb_stb_o => wb_stb_o, -- strobe
|
wb_stb_o => wb_stb_o, -- strobe
|
wb_cyc_o => wb_cyc_o, -- valid cycle
|
wb_cyc_o => wb_cyc_o, -- valid cycle
|
wb_lock_o => wb_lock_o, -- locked/exclusive bus access
|
wb_tag_i => wb_tag_i, -- response tag
|
wb_ack_i => wb_ack_i, -- transfer acknowledge
|
wb_ack_i => wb_ack_i, -- transfer acknowledge
|
wb_err_i => wb_err_i -- transfer error
|
wb_err_i => wb_err_i -- transfer error
|
);
|
);
|
end generate;
|
end generate;
|
|
|
neorv32_wishbone_inst_false:
|
neorv32_wishbone_inst_false:
|
if (MEM_EXT_EN = false) generate
|
if (MEM_EXT_EN = false) generate
|
wishbone_rdata <= (others => '0');
|
wishbone_rdata <= (others => '0');
|
wishbone_ack <= '0';
|
wishbone_ack <= '0';
|
wishbone_err <= '0';
|
wishbone_err <= '0';
|
|
wishbone_exclr <= '0';
|
--
|
--
|
wb_adr_o <= (others => '0');
|
wb_adr_o <= (others => '0');
|
wb_dat_o <= (others => '0');
|
wb_dat_o <= (others => '0');
|
wb_we_o <= '0';
|
wb_we_o <= '0';
|
wb_sel_o <= (others => '0');
|
wb_sel_o <= (others => '0');
|
wb_stb_o <= '0';
|
wb_stb_o <= '0';
|
wb_cyc_o <= '0';
|
wb_cyc_o <= '0';
|
wb_lock_o <= '0';
|
|
wb_tag_o <= (others => '0');
|
wb_tag_o <= (others => '0');
|
end generate;
|
end generate;
|
|
|
|
|
-- IO Access? -----------------------------------------------------------------------------
|
-- IO Access? -----------------------------------------------------------------------------
|
