| Line 118... |
Line 118... |
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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| Line 328... |
Line 332... |
signal slink_rx_irq : std_ulogic;
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signal slink_rx_irq : std_ulogic;
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signal xirq_irq : std_ulogic;
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signal xirq_irq : std_ulogic;
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-- misc --
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-- misc --
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal mtime_time : std_ulogic_vector(63 downto 0); -- current system time from MTIME
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signal cpu_sleep : std_ulogic; -- CPU is in sleep mode when set
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signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
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signal bus_keeper_err : std_ulogic; -- bus keeper: bus access timeout
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begin
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begin
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|
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-- Processor IO/Peripherals Configuration -------------------------------------------------
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-- Processor IO/Peripherals Configuration -------------------------------------------------
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| Line 477... |
Line 480... |
)
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)
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port map (
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port map (
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-- global control --
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-- global control --
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clk_i => clk_i, -- global clock, rising edge
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clk_i => clk_i, -- global clock, rising edge
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rstn_i => sys_rstn, -- global reset, low-active, async
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rstn_i => sys_rstn, -- global reset, low-active, async
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sleep_o => cpu_sleep, -- cpu is in sleep mode when set
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sleep_o => open, -- cpu is in sleep mode when set
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-- instruction bus interface --
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-- instruction bus interface --
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i_bus_addr_o => cpu_i.addr, -- bus access address
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i_bus_addr_o => cpu_i.addr, -- bus access address
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i_bus_rdata_i => cpu_i.rdata, -- bus read data
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i_bus_rdata_i => cpu_i.rdata, -- bus read data
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i_bus_wdata_o => cpu_i.wdata, -- bus write data
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i_bus_wdata_o => cpu_i.wdata, -- bus write data
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i_bus_ben_o => cpu_i.ben, -- byte enable
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i_bus_ben_o => cpu_i.ben, -- byte enable
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| Line 866... |
Line 869... |
data_o => resp_bus(RESP_CFS).rdata, -- data out
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data_o => resp_bus(RESP_CFS).rdata, -- data out
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ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge
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ack_o => resp_bus(RESP_CFS).ack, -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o => cfs_cg_en, -- enable clock generator
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clkgen_en_o => cfs_cg_en, -- enable clock generator
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clkgen_i => clk_gen, -- "clock" inputs
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clkgen_i => clk_gen, -- "clock" inputs
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-- CPU state --
|
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sleep_i => cpu_sleep, -- set if cpu is in sleep mode
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-- interrupt --
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-- interrupt --
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irq_o => cfs_irq, -- interrupt request
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irq_o => cfs_irq, -- interrupt request
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-- custom io (conduit) --
|
-- custom io (conduit) --
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cfs_in_i => cfs_in_i, -- custom inputs
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cfs_in_i => cfs_in_i, -- custom inputs
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cfs_out_o => cfs_out_o -- custom outputs
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cfs_out_o => cfs_out_o -- custom outputs
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| Line 1004... |
Line 1005... |
-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_uart0_inst_true:
|
neorv32_uart0_inst_true:
|
if (IO_UART0_EN = true) generate
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if (IO_UART0_EN = true) generate
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neorv32_uart0_inst: neorv32_uart
|
neorv32_uart0_inst: neorv32_uart
|
generic map (
|
generic map (
|
UART_PRIMARY => true -- true = primary UART (UART0), false = secondary UART (UART1)
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UART_PRIMARY => true, -- true = primary UART (UART0), false = secondary UART (UART1)
|
|
UART_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
|
UART_TX_FIFO => IO_UART0_TX_FIFO -- TX fifo depth, has to be a power of two, min 1
|
)
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)
|
port map (
|
port map (
|
-- host access --
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-- host access --
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clk_i => clk_i, -- global clock line
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clk_i => clk_i, -- global clock line
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addr_i => p_bus.addr, -- address
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addr_i => p_bus.addr, -- address
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| Line 1048... |
Line 1051... |
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
neorv32_uart1_inst_true:
|
neorv32_uart1_inst_true:
|
if (IO_UART1_EN = true) generate
|
if (IO_UART1_EN = true) generate
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neorv32_uart1_inst: neorv32_uart
|
neorv32_uart1_inst: neorv32_uart
|
generic map (
|
generic map (
|
UART_PRIMARY => false -- true = primary UART (UART0), false = secondary UART (UART1)
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UART_PRIMARY => false, -- true = primary UART (UART0), false = secondary UART (UART1)
|
|
UART_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
|
UART_TX_FIFO => IO_UART1_TX_FIFO -- TX fifo depth, has to be a power of two, min 1
|
)
|
)
|
port map (
|
port map (
|
-- host access --
|
-- host access --
|
clk_i => clk_i, -- global clock line
|
clk_i => clk_i, -- global clock line
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addr_i => p_bus.addr, -- address
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addr_i => p_bus.addr, -- address
|
| Line 1154... |
Line 1159... |
end generate;
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end generate;
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|
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neorv32_twi_inst_false:
|
neorv32_twi_inst_false:
|
if (IO_TWI_EN = false) generate
|
if (IO_TWI_EN = false) generate
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resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c;
|
resp_bus(RESP_TWI) <= resp_bus_entry_terminate_c;
|
-- twi_sda_io <= 'Z'; -- FIXME?
|
twi_sda_io <= 'Z';
|
-- twi_scl_io <= 'Z'; -- FIXME?
|
twi_scl_io <= 'Z';
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twi_cg_en <= '0';
|
twi_cg_en <= '0';
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twi_irq <= '0';
|
twi_irq <= '0';
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end generate;
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end generate;
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