| Line 244... |
Line 244... |
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-- helpers --
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-- helpers --
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constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all?
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constant io_slink_en_c : boolean := boolean(SLINK_NUM_RX > 0) or boolean(SLINK_NUM_TX > 0); -- implement slink at all?
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-- reset generator --
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-- reset generator --
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signal rstn_gen : std_ulogic_vector(7 downto 0) := (others => '0'); -- initialize (=reset) via bitstream (for FPGAs only)
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signal ext_rstn_sync : std_ulogic_vector(3 downto 0) := (others => '0'); -- initialize (=reset) via bitstream (for FPGAs only)
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signal ext_rstn : std_ulogic;
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signal ext_rstn : std_ulogic;
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signal sys_rstn : std_ulogic;
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signal sys_rstn : std_ulogic;
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signal wdt_rstn : std_ulogic;
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signal wdt_rstn : std_ulogic;
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-- clock generator --
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-- clock generator --
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Line 415... |
-- Reset Generator ------------------------------------------------------------------------
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-- Reset Generator ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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reset_generator: process(rstn_i, clk_i)
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reset_generator: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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rstn_gen <= (others => '0');
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ext_rstn_sync <= (others => '0');
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ext_rstn <= '0';
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sys_rstn <= '0';
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sys_rstn <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- keep internal reset active for at least <rstn_gen'size> clock cycles --
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-- keep internal reset active for at least <ext_rstn_sync'size> clock cycles --
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rstn_gen <= rstn_gen(rstn_gen'left-1 downto 0) & '1';
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ext_rstn_sync <= ext_rstn_sync(ext_rstn_sync'left-1 downto 0) & '1';
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-- beautified external reset signal --
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if (and_reduce_f(ext_rstn_sync) = '1') then
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ext_rstn <= '1';
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else
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ext_rstn <= '0';
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end if;
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-- system reset: can also be triggered by watchdog and debug module --
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-- system reset: can also be triggered by watchdog and debug module --
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sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn;
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sys_rstn <= ext_rstn and wdt_rstn and dci_ndmrstn;
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end if;
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end if;
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end process reset_generator;
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end process reset_generator;
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-- beautified external reset signal --
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ext_rstn <= rstn_gen(rstn_gen'left);
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-- Clock Generator ------------------------------------------------------------------------
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-- Clock Generator ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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clock_generator: process(sys_rstn, clk_i)
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clock_generator: process(sys_rstn, clk_i)
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begin
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begin
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if (sys_rstn = '0') then
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if (sys_rstn = '0') then
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clk_gen_en_ff <= '-';
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clk_gen_en_ff <= '0';
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clk_div_ff <= (others => '-');
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clk_div <= (others => '0');
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clk_div <= (others => '0'); -- reset required
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clk_div_ff <= (others => '0');
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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clk_gen_en_ff <= or_reduce_f(clk_gen_en);
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clk_gen_en_ff <= or_reduce_f(clk_gen_en);
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clk_div_ff <= clk_div;
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if (clk_gen_en_ff = '1') then
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if (clk_gen_en_ff = '1') then -- actual clock generator
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clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
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clk_div <= std_ulogic_vector(unsigned(clk_div) + 1);
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else
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clk_div <= (others => '0');
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end if;
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end if;
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clk_div_ff <= clk_div;
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end if;
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end if;
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end process clock_generator;
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end process clock_generator;
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-- clock enables: rising edge detectors --
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-- clock enables: rising edge detectors --
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clk_gen(clk_div2_c) <= clk_div(0) and (not clk_div_ff(0)); -- CLK/2
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clk_gen(clk_div2_c) <= clk_div(0) and (not clk_div_ff(0)); -- CLK/2
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Line 948... |
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-- IO Access? -----------------------------------------------------------------------------
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-- IO Access? -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
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io_acc <= '1' when (p_bus.addr(data_width_c-1 downto index_size_f(io_size_c)) = io_base_c(data_width_c-1 downto index_size_f(io_size_c))) else '0';
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io_rden <= io_acc and p_bus.re;
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io_rden <= '1' when (io_acc = '1') and (p_bus.re = '1') else '0';
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io_wren <= io_acc and p_bus.we and and_reduce_f(p_bus.ben); -- only full-word write accesses are allowed (reduces HW complexity)
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io_wren <= '1' when (io_acc = '1') and (p_bus.we = '1') and (p_bus.ben = "1111") else '0'; -- only full-word write accesses are allowed (reduces HW complexity)
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-- Custom Functions Subsystem (CFS) -------------------------------------------------------
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-- Custom Functions Subsystem (CFS) -------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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neorv32_cfs_inst_true:
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neorv32_cfs_inst_true:
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