| Line 62... |
Line 62... |
-- host access --
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic -- transfer acknowledge
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ack_o : out std_ulogic -- transfer acknowledge
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);
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);
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end neorv32_trng;
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end neorv32_trng;
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| Line 132... |
Line 131... |
if rising_edge(clk_i) then
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if rising_edge(clk_i) then
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ack_o <= acc_en and (rden_i or wren_i);
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ack_o <= acc_en and (rden_i or wren_i);
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-- write access --
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-- write access --
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if (wren = '1') then
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if (wren = '1') then
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if (addr = trng_ctrl_addr_c) then
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if (addr = trng_ctrl_addr_c) then
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if (ben_i(0) = '1') then
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tap_config <= data_i(tap_config'left downto 0);
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tap_config(07 downto 00) <= data_i(ctrl_taps_lsb_c+7 downto ctrl_taps_lsb_c+0);
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end if;
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if (ben_i(1) = '1') then
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tap_config(15 downto 08) <= data_i(ctrl_taps_lsb_c+15 downto ctrl_taps_lsb_c+8);
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end if;
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-- if (ben_i(2) = '1') then
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-- NULL;
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-- end if;
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if (ben_i(3) = '1') then
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rnd_enable <= data_i(ctrl_en_c);
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rnd_enable <= data_i(ctrl_en_c);
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end if;
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rden = '1') then
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if (rden = '1') then
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if (addr = trng_ctrl_addr_c) then
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if (addr = trng_ctrl_addr_c) then
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data_o(ctrl_taps_msb_c downto ctrl_taps_lsb_c) <= tap_config;
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data_o(ctrl_taps_msb_c downto ctrl_taps_lsb_c) <= tap_config;
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