| Line 5... |
Line 5... |
-- # Supports ACKs by the constroller. No multi-controller support and no peripheral mode support #
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-- # Supports ACKs by the constroller. No multi-controller support and no peripheral mode support #
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-- # yet. Interrupt: TWI_transfer_done #
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-- # yet. Interrupt: TWI_transfer_done #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 58... |
Line 58... |
clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- com lines --
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-- com lines --
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twi_sda_io : inout std_logic; -- serial data line
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twi_sda_io : inout std_logic; -- serial data line
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twi_scl_io : inout std_logic; -- serial clock line
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twi_scl_io : inout std_logic; -- serial clock line
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-- interrupt --
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-- interrupt --
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twi_irq_o : out std_ulogic -- transfer done IRQ
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irq_o : out std_ulogic -- transfer done IRQ
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);
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);
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end neorv32_twi;
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end neorv32_twi;
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architecture neorv32_twi_rtl of neorv32_twi is
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architecture neorv32_twi_rtl of neorv32_twi is
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| Line 72... |
Line 72... |
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-- control reg bits --
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-- control reg bits --
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constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
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constant ctrl_twi_en_c : natural := 0; -- r/w: TWI enable
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constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
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constant ctrl_twi_start_c : natural := 1; -- -/w: Generate START condition
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constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
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constant ctrl_twi_stop_c : natural := 2; -- -/w: Generate STOP condition
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constant ctrl_twi_irq_en_c : natural := 3; -- r/w: Enable transmission done interrupt
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constant ctrl_twi_prsc0_c : natural := 3; -- r/w: CLK prsc bit 0
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constant ctrl_twi_prsc0_c : natural := 4; -- r/w: CLK prsc bit 0
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constant ctrl_twi_prsc1_c : natural := 4; -- r/w: CLK prsc bit 1
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constant ctrl_twi_prsc1_c : natural := 5; -- r/w: CLK prsc bit 1
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constant ctrl_twi_prsc2_c : natural := 5; -- r/w: CLK prsc bit 2
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constant ctrl_twi_prsc2_c : natural := 6; -- r/w: CLK prsc bit 2
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constant ctrl_twi_mack_c : natural := 6; -- r/w: generate ACK by controller for transmission
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constant ctrl_twi_mack_c : natural := 7; -- r/w: generate ACK by controller for transmission
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constant ctrl_twi_cksten_c : natural := 7; -- r/w: enable clock stretching by peripheral
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constant ctrl_twi_cksten_c : natural := 8; -- r/w: enable clock stretching by peripheral
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--
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--
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constant ctrl_twi_ack_c : natural := 30; -- r/-: Set if ACK received
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constant ctrl_twi_ack_c : natural := 30; -- r/-: Set if ACK received
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constant ctrl_twi_busy_c : natural := 31; -- r/-: Set if TWI unit is busy
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constant ctrl_twi_busy_c : natural := 31; -- r/-: Set if TWI unit is busy
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-- access control --
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-- access control --
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| Line 97... |
Line 96... |
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-- twi clock stretching --
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-- twi clock stretching --
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signal twi_clk_halt : std_ulogic;
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signal twi_clk_halt : std_ulogic;
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-- twi transceiver core --
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-- twi transceiver core --
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signal ctrl : std_ulogic_vector(8 downto 0); -- unit's control register
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signal ctrl : std_ulogic_vector(7 downto 0); -- unit's control register
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signal arbiter : std_ulogic_vector(2 downto 0);
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signal arbiter : std_ulogic_vector(2 downto 0);
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signal twi_bitcnt : std_ulogic_vector(3 downto 0);
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signal twi_bitcnt : std_ulogic_vector(3 downto 0);
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signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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signal twi_rtx_sreg : std_ulogic_vector(8 downto 0); -- main rx/tx shift reg
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-- tri-state I/O --
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-- tri-state I/O --
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| Line 135... |
Line 134... |
-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rd_en = '1') then
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if (rd_en = '1') then
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if (addr = twi_ctrl_addr_c) then
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if (addr = twi_ctrl_addr_c) then
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data_o(ctrl_twi_en_c) <= ctrl(ctrl_twi_en_c);
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data_o(ctrl_twi_en_c) <= ctrl(ctrl_twi_en_c);
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data_o(ctrl_twi_irq_en_c) <= ctrl(ctrl_twi_irq_en_c);
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data_o(ctrl_twi_prsc0_c) <= ctrl(ctrl_twi_prsc0_c);
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data_o(ctrl_twi_prsc0_c) <= ctrl(ctrl_twi_prsc0_c);
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data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
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data_o(ctrl_twi_prsc1_c) <= ctrl(ctrl_twi_prsc1_c);
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data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
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data_o(ctrl_twi_prsc2_c) <= ctrl(ctrl_twi_prsc2_c);
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data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
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data_o(ctrl_twi_mack_c) <= ctrl(ctrl_twi_mack_c);
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data_o(ctrl_twi_cksten_c) <= ctrl(ctrl_twi_cksten_c);
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data_o(ctrl_twi_cksten_c) <= ctrl(ctrl_twi_cksten_c);
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| Line 191... |
Line 189... |
twi_sda_i_ff1 <= twi_sda_i_ff0;
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twi_sda_i_ff1 <= twi_sda_i_ff0;
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twi_scl_i_ff0 <= twi_scl_i;
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twi_scl_i_ff0 <= twi_scl_i;
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twi_scl_i_ff1 <= twi_scl_i_ff0;
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twi_scl_i_ff1 <= twi_scl_i_ff0;
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-- defaults --
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-- defaults --
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twi_irq_o <= '0';
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irq_o <= '0';
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arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
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arbiter(2) <= ctrl(ctrl_twi_en_c); -- still activated?
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-- serial engine --
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-- serial engine --
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-- TWI bus signals are set/sampled using 4 clock phases
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-- TWI bus signals are set/sampled using 4 clock phases
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case arbiter is
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case arbiter is
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| Line 257... |
Line 255... |
twi_scl_o <= '0';
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twi_scl_o <= '0';
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end if;
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end if;
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if (twi_bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
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if (twi_bitcnt = "1010") then -- 8 data bits + 1 bit for ACK + 1 tick delay
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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arbiter(1 downto 0) <= "00"; -- go back to IDLE
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twi_irq_o <= ctrl(ctrl_twi_irq_en_c); -- fire IRQ if enabled
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irq_o <= '1'; -- fire IRQ
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end if;
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end if;
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when others => -- "0--" OFFLINE: TWI deactivated
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when others => -- "0--" OFFLINE: TWI deactivated
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twi_sda_o <= '1';
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twi_sda_o <= '1';
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twi_scl_o <= '1';
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twi_scl_o <= '1';
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