| Line 13... |
Line 13... |
-- # "neorv32.uart.sim_mode.text.out". The full 32-bit write data is also stored as 8-hex char #
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-- # "neorv32.uart.sim_mode.text.out". The full 32-bit write data is also stored as 8-hex char #
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-- # encoded value to text file "neorv32.uart.sim_mode.data.out". #
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-- # encoded value to text file "neorv32.uart.sim_mode.data.out". #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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| Line 67... |
Line 67... |
clkgen_i : in std_ulogic_vector(07 downto 0);
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- com lines --
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-- com lines --
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uart_txd_o : out std_ulogic;
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uart_txd_o : out std_ulogic;
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uart_rxd_i : in std_ulogic;
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uart_rxd_i : in std_ulogic;
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-- interrupts --
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-- interrupts --
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uart_irq_o : out std_ulogic -- uart rx/tx interrupt
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irq_rxd_o : out std_ulogic; -- uart data received interrupt
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irq_txd_o : out std_ulogic -- uart transmission done interrupt
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);
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);
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end neorv32_uart;
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end neorv32_uart;
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architecture neorv32_uart_rtl of neorv32_uart is
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architecture neorv32_uart_rtl of neorv32_uart is
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| Line 109... |
Line 110... |
constant ctrl_uart_prsc0_c : natural := 24; -- r/w: UART baud prsc bit 0
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constant ctrl_uart_prsc0_c : natural := 24; -- r/w: UART baud prsc bit 0
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constant ctrl_uart_prsc1_c : natural := 25; -- r/w: UART baud prsc bit 1
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constant ctrl_uart_prsc1_c : natural := 25; -- r/w: UART baud prsc bit 1
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constant ctrl_uart_prsc2_c : natural := 26; -- r/w: UART baud prsc bit 2
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constant ctrl_uart_prsc2_c : natural := 26; -- r/w: UART baud prsc bit 2
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--
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--
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constant ctrl_uart_en_c : natural := 28; -- r/w: UART enable
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constant ctrl_uart_en_c : natural := 28; -- r/w: UART enable
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constant ctrl_uart_rx_irq_c : natural := 29; -- r/w: UART rx done interrupt enable
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constant ctrl_uart_tx_irq_c : natural := 30; -- r/w: UART tx done interrupt enable
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constant ctrl_uart_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy
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constant ctrl_uart_tx_busy_c : natural := 31; -- r/-: UART transmitter is busy
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-- data register flags --
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-- data register flags --
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constant data_rx_avail_c : natural := 31; -- r/-: Rx data available
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constant data_rx_avail_c : natural := 31; -- r/-: Rx data available
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constant data_rx_overr_c : natural := 30; -- r/-: Rx data overrun
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constant data_rx_overr_c : natural := 30; -- r/-: Rx data overrun
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| Line 181... |
Line 180... |
ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= data_i(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= data_i(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c);
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ctrl(ctrl_uart_sim_en_c) <= data_i(ctrl_uart_sim_en_c);
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ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= data_i(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
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ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= data_i(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
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ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= data_i(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
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ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= data_i(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
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ctrl(ctrl_uart_en_c) <= data_i(ctrl_uart_en_c);
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ctrl(ctrl_uart_en_c) <= data_i(ctrl_uart_en_c);
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ctrl(ctrl_uart_rx_irq_c) <= data_i(ctrl_uart_rx_irq_c);
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ctrl(ctrl_uart_tx_irq_c) <= data_i(ctrl_uart_tx_irq_c);
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end if;
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end if;
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end if;
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end if;
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-- read access --
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-- read access --
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data_o <= (others => '0');
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data_o <= (others => '0');
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if (rd_en = '1') then
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if (rd_en = '1') then
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| Line 194... |
Line 191... |
data_o(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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data_o(ctrl_uart_baud11_c downto ctrl_uart_baud00_c) <= ctrl(ctrl_uart_baud11_c downto ctrl_uart_baud00_c);
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data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c);
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data_o(ctrl_uart_sim_en_c) <= ctrl(ctrl_uart_sim_en_c);
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data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
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data_o(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c) <= ctrl(ctrl_uart_pmode1_c downto ctrl_uart_pmode0_c);
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data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
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data_o(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c) <= ctrl(ctrl_uart_prsc2_c downto ctrl_uart_prsc0_c);
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data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
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data_o(ctrl_uart_en_c) <= ctrl(ctrl_uart_en_c);
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data_o(ctrl_uart_rx_irq_c) <= ctrl(ctrl_uart_rx_irq_c);
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data_o(ctrl_uart_tx_irq_c) <= ctrl(ctrl_uart_tx_irq_c);
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data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
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data_o(ctrl_uart_tx_busy_c) <= uart_tx.busy;
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else -- uart_rtx_addr_c
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else -- uart_rtx_addr_c
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data_o(data_rx_avail_c) <= uart_rx.avail(0);
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data_o(data_rx_avail_c) <= uart_rx.avail(0);
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data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1);
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data_o(data_rx_overr_c) <= uart_rx.avail(0) and uart_rx.avail(1);
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data_o(data_rx_ferr_c) <= uart_rx.ferr;
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data_o(data_rx_ferr_c) <= uart_rx.ferr;
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| Line 315... |
Line 310... |
end process uart_rx_unit;
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end process uart_rx_unit;
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-- Interrupt ------------------------------------------------------------------------------
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-- Interrupt ------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- UART Rx data available [OR] UART Tx complete
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-- UART Rx data available
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uart_irq_o <= (uart_rx.busy_ff and (not uart_rx.busy) and ctrl(ctrl_uart_rx_irq_c)) or (uart_tx.done and ctrl(ctrl_uart_tx_irq_c));
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irq_rxd_o <= uart_rx.busy_ff and (not uart_rx.busy);
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-- UART Tx complete
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irq_txd_o <= uart_tx.done;
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-- SIMULATION Output ----------------------------------------------------------------------
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-- SIMULATION Output ----------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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sim_output: process(clk_i) -- for SIMULATION ONLY!
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sim_output: process(clk_i) -- for SIMULATION ONLY!
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