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Line 52... |
clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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rstn_i : in std_ulogic; -- global reset line, low-active
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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-- clock generator --
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_en_o : out std_ulogic; -- enable clock generator
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begin
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begin
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
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pwd_ok <= '1' when (data_i(15 downto 8) = wdt_password_c) and (ben_i(1) = '1') else '0'; -- password check
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pwd_ok <= '1' when (data_i(15 downto 8) = wdt_password_c) else '0'; -- password check
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wren <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- write access ok
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wren <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '1')) else '0'; -- write access ok
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fail <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '0')) else '0'; -- write access fail!
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fail <= '1' when ((acc_en = '1') and (wren_i = '1') and (pwd_ok = '0')) else '0'; -- write access fail!
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-- Write Access, Reset Generator ----------------------------------------------------------
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-- Write Access, Reset Generator ----------------------------------------------------------
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clk_sel <= (others => '1'); -- slowest clock rst_source
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clk_sel <= (others => '1'); -- slowest clock rst_source
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rst_gen <= (others => '1'); -- do NOT fire on reset!
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rst_gen <= (others => '1'); -- do NOT fire on reset!
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else
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else
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-- control register write access --
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-- control register write access --
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if (wren = '1') then -- allow write if password is correct
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if (wren = '1') then -- allow write if password is correct
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if (ben_i(0) = '1') then
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enable <= data_i(ctrl_enable_c);
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enable <= data_i(ctrl_enable_c);
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clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
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clk_sel <= data_i(ctrl_clksel2_c downto ctrl_clksel0_c);
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mode <= data_i(ctrl_mode_c);
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mode <= data_i(ctrl_mode_c);
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end if;
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end if;
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end if;
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-- trigger system reset when enabled AND reset mode AND timeout OR unauthorized access --
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-- trigger system reset when enabled AND reset mode AND timeout OR unauthorized access --
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if (enable = '1') and (mode = '1') and ((cnt(cnt'left) = '1') or (fail_ff = '1')) then
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if (enable = '1') and (mode = '1') and ((cnt(cnt'left) = '1') or (fail_ff = '1')) then
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rst_gen <= (others => '0');
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rst_gen <= (others => '0');
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else
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else
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rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
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rst_gen <= rst_gen(rst_gen'left-1 downto 0) & '1';
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