| Line 110... |
Line 110... |
signal rst_gen : std_ulogic_vector(03 downto 0);
|
signal rst_gen : std_ulogic_vector(03 downto 0);
|
|
|
-- internal reset (sync, low-active) --
|
-- internal reset (sync, low-active) --
|
signal rstn_sync : std_ulogic;
|
signal rstn_sync : std_ulogic;
|
|
|
|
-- cpu interrupt --
|
|
type cpu_irq_t is record
|
|
pending : std_ulogic;
|
|
set : std_ulogic;
|
|
clr : std_ulogic;
|
|
end record;
|
|
signal cpu_irq : cpu_irq_t;
|
|
|
begin
|
begin
|
|
|
-- Access Control -------------------------------------------------------------------------
|
-- Access Control -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
|
acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
|
| Line 130... |
Line 138... |
ctrl_reg.enforce <= '0';
|
ctrl_reg.enforce <= '0';
|
ctrl_reg.enable <= '0'; -- disable WDT
|
ctrl_reg.enable <= '0'; -- disable WDT
|
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
|
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
|
ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
|
ctrl_reg.clk_sel <= (others => '1'); -- slowest clock source
|
ctrl_reg.lock <= '0';
|
ctrl_reg.lock <= '0';
|
|
cpu_irq.clr <= '-';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
|
-- acknowledge interrupt when resetting WDT --
|
|
cpu_irq.clr <= ctrl_reg.reset;
|
if (rstn_sync = '0') then -- internal reset
|
if (rstn_sync = '0') then -- internal reset
|
ctrl_reg.reset <= '0';
|
ctrl_reg.reset <= '0';
|
ctrl_reg.enforce <= '0';
|
ctrl_reg.enforce <= '0';
|
ctrl_reg.enable <= '0'; -- disable WDT
|
ctrl_reg.enable <= '0'; -- disable WDT
|
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
|
ctrl_reg.mode <= '0'; -- trigger interrupt on WDT overflow
|
| Line 176... |
Line 187... |
end if;
|
end if;
|
end if;
|
end if;
|
end process wdt_counter;
|
end process wdt_counter;
|
|
|
-- action trigger --
|
-- action trigger --
|
irq_o <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and (not ctrl_reg.mode); -- mode 0: IRQ
|
cpu_irq.set <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and (not ctrl_reg.mode); -- mode 0: IRQ
|
hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and ( ctrl_reg.mode); -- mode 1: RESET
|
hw_rst <= ctrl_reg.enable and (wdt_cnt(wdt_cnt'left) or ctrl_reg.enforce) and ( ctrl_reg.mode); -- mode 1: RESET
|
|
|
|
|
|
-- Interrupt ------------------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
irq_gen: process(clk_i)
|
|
begin
|
|
if rising_edge(clk_i) then
|
|
if (ctrl_reg.enable = '0') then
|
|
cpu_irq.pending <= '0';
|
|
else
|
|
if (cpu_irq.set = '1') then
|
|
cpu_irq.pending <= '1';
|
|
elsif(cpu_irq.clr = '1') then
|
|
cpu_irq.pending <= '0';
|
|
else
|
|
cpu_irq.pending <= cpu_irq.pending;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
end process irq_gen;
|
|
|
|
-- CPU IRQ --
|
|
irq_o <= cpu_irq.pending;
|
|
|
|
|
-- Reset Generator & Action Cause Indicator -----------------------------------------------
|
-- Reset Generator & Action Cause Indicator -----------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
reset_generator: process(rstn_i, clk_i)
|
reset_generator: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
