| Line 2... |
Line 2... |
-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The interface is either unregistered (INTERFACE_REG_STAGES = 0), only outgoing signals are #
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-- # The interface is either unregistered (INTERFACE_REG_STAGES = 0), only outgoing signals are #
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-- # registered (INTERFACE_REG_STAGES = 1) or incoming and outgoing signals are registered #
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-- # registered (INTERFACE_REG_STAGES = 1) or incoming and outgoing signals are registered #
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-- # (INTERFACE_REG_STAGES = 2). #
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-- # (INTERFACE_REG_STAGES = 2). #
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-- # #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
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-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
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-- # loader or the internal instruction & data memories (if implemented), are delegated via this #
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-- # loader or the internal instruction or data memories (if implemented), are delegated via this #
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-- # Wishbone gateway to the external bus interface. #
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-- # Wishbone gateway to the external bus interface. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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| Line 48... |
Line 48... |
use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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|
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entity neorv32_wishbone is
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entity neorv32_wishbone is
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generic (
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generic (
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INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
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INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
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-- Memory configuration: Instruction memory --
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-- Internal instruction memory --
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MEM_ISPACE_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address of instruction memory space
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MEM_ISPACE_SIZE : natural := 8*1024; -- total size of instruction memory space in byte
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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-- Memory configuration: Data memory --
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-- Internal data memory --
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MEM_DSPACE_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address of data memory space
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MEM_DSPACE_SIZE : natural := 4*1024; -- total size of data memory space in byte
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural := 4*1024 -- size of processor-internal data memory in bytes
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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| Line 91... |
Line 87... |
architecture neorv32_wishbone_rtl of neorv32_wishbone is
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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-- access control --
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-- access control --
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signal int_imem_acc, int_imem_acc_real : std_ulogic;
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signal int_imem_acc, int_imem_acc_real : std_ulogic;
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signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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signal int_boot_acc, int_io_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal wb_access : std_ulogic;
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signal wb_access : std_ulogic;
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signal wb_access_ff, wb_access_ff_ff : std_ulogic;
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signal rb_en : std_ulogic;
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-- bus arbiter --
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-- bus arbiter --
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signal wb_stb_ff0 : std_ulogic;
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signal wb_stb_ff0 : std_ulogic;
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signal wb_stb_ff1 : std_ulogic;
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signal wb_stb_ff1 : std_ulogic;
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signal wb_cyc_ff : std_ulogic;
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signal wb_cyc_ff : std_ulogic;
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signal wb_ack_ff : std_ulogic;
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signal wb_ack_ff : std_ulogic;
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signal wb_err_ff : std_ulogic;
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signal wb_err_ff : std_ulogic;
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-- data read-back --
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signal wb_rdata : std_ulogic_vector(31 downto 0);
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begin
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begin
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|
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-- Sanity Check ---------------------------------------------------------------------------
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-- Sanity Check ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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sanity_check: process(clk_i)
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assert (INTERFACE_REG_STAGES <= 2) report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error;
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begin
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assert (INTERFACE_REG_STAGES /= 0) report "NEORV32 CONFIG WARNING! External memory interface without register stages is still experimental for peripherals with more than 1 cycle latency." severity warning;
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if rising_edge(clk_i) then
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if (INTERFACE_REG_STAGES > 2) then
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assert false report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error;
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end if;
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end if;
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end process sanity_check;
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- access to internal IMEM or DMEM? --
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-- access to internal IMEM or DMEM? --
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int_imem_acc <= '1' when (addr_i >= MEM_ISPACE_BASE) and (addr_i < std_ulogic_vector(unsigned(MEM_ISPACE_BASE) + MEM_INT_IMEM_SIZE)) else '0';
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int_imem_acc <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + MEM_INT_IMEM_SIZE)) else '0';
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int_dmem_acc <= '1' when (addr_i >= MEM_DSPACE_BASE) and (addr_i < std_ulogic_vector(unsigned(MEM_DSPACE_BASE) + MEM_INT_DMEM_SIZE)) else '0';
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int_dmem_acc <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + MEM_INT_DMEM_SIZE)) else '0';
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int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
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int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
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int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
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int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
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int_boot_acc <= '1' when (addr_i >= boot_base_c) else '0';
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int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
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int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
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--int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
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-- actual external bus access? --
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-- actual external bus access? --
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wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc) and (not int_io_acc) and (wren_i or rden_i);
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wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc) and (wren_i or rden_i);
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_arbiter: process(rstn_i, clk_i)
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bus_arbiter: process(rstn_i, clk_i)
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| Line 139... |
Line 134... |
wb_cyc_ff <= '0';
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wb_cyc_ff <= '0';
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wb_stb_ff1 <= '0';
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wb_stb_ff1 <= '0';
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wb_stb_ff0 <= '0';
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wb_stb_ff0 <= '0';
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wb_ack_ff <= '0';
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wb_ack_ff <= '0';
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wb_err_ff <= '0';
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wb_err_ff <= '0';
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wb_access_ff <= '0';
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wb_access_ff_ff <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- bus cycle --
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-- bus cycle --
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if (INTERFACE_REG_STAGES = 0) then
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if (INTERFACE_REG_STAGES = 0) then
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wb_cyc_ff <= '0'; -- unused
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wb_cyc_ff <= '0'; -- unused
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else
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else
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wb_cyc_ff <= (wb_cyc_ff or wb_access) and ((not wb_ack_i) or (not wb_err_i)) and (not cancel_i);
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wb_cyc_ff <= (wb_cyc_ff or wb_access) and (not wb_ack_i) and (not wb_err_i) and (not cancel_i);
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end if;
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end if;
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-- bus strobe --
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-- bus strobe --
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wb_stb_ff1 <= wb_stb_ff0;
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wb_stb_ff1 <= wb_stb_ff0;
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wb_stb_ff0 <= wb_access;
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wb_stb_ff0 <= wb_access;
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-- bus ack --
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-- bus ack --
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wb_ack_ff <= wb_ack_i;
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wb_ack_ff <= wb_ack_i;
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-- bus err --
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-- bus err --
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wb_err_ff <= wb_err_i;
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wb_err_ff <= wb_err_i;
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-- access still active? --
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wb_access_ff_ff <= wb_access_ff;
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if (wb_access = '1') then
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wb_access_ff <= '1';
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elsif ((wb_ack_i or wb_err_i or cancel_i) = '1') then
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wb_access_ff <= '0';
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end if;
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end if;
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end if;
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end process bus_arbiter;
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end process bus_arbiter;
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-- bus cycle --
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-- bus cycle --
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wb_cyc_o <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff;
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wb_cyc_o <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff;
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| Line 168... |
Line 172... |
ack_o <= wb_ack_ff when (INTERFACE_REG_STAGES = 2) else wb_ack_i;
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ack_o <= wb_ack_ff when (INTERFACE_REG_STAGES = 2) else wb_ack_i;
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-- cpu err --
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-- cpu err --
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err_o <= wb_err_ff when (INTERFACE_REG_STAGES = 2) else wb_err_i;
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err_o <= wb_err_ff when (INTERFACE_REG_STAGES = 2) else wb_err_i;
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-- cpu read-data --
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rb_en <= wb_access_ff_ff when (INTERFACE_REG_STAGES = 2) else wb_access_ff;
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data_o <= wb_rdata when (rb_en = '1') else (others => '0');
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-- Bus Buffer -----------------------------------------------------------------------------
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-- Bus Buffer -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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interface_reg_level_zero:
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interface_reg_level_zero:
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if (INTERFACE_REG_STAGES = 0) generate -- 0 register levels: direct connection
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if (INTERFACE_REG_STAGES = 0) generate -- 0 register levels: direct connection
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data_o <= wb_dat_i;
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wb_rdata <= wb_dat_i;
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wb_adr_o <= addr_i;
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wb_adr_o <= addr_i;
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wb_dat_o <= data_i;
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wb_dat_o <= data_i;
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wb_sel_o <= ben_i;
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wb_sel_o <= ben_i;
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wb_we_o <= wren_i;
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wb_we_o <= wren_i;
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end generate;
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end generate;
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| Line 193... |
Line 201... |
wb_sel_o <= ben_i;
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wb_sel_o <= ben_i;
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wb_we_o <= wren_i;
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wb_we_o <= wren_i;
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end if;
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end if;
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end if;
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end if;
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end process buffer_stages_one;
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end process buffer_stages_one;
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data_o <= wb_dat_i;
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wb_rdata <= wb_dat_i;
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end generate;
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end generate;
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|
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interface_reg_level_two:
|
interface_reg_level_two:
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if (INTERFACE_REG_STAGES = 2) generate -- 2 register levels: buffer incoming and outgoing signals
|
if (INTERFACE_REG_STAGES = 2) generate -- 2 register levels: buffer incoming and outgoing signals
|
buffer_stages_two: process(clk_i)
|
buffer_stages_two: process(clk_i)
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| Line 206... |
Line 214... |
if (wb_cyc_ff = '0') then
|
if (wb_cyc_ff = '0') then
|
wb_adr_o <= addr_i;
|
wb_adr_o <= addr_i;
|
wb_dat_o <= data_i;
|
wb_dat_o <= data_i;
|
wb_sel_o <= ben_i;
|
wb_sel_o <= ben_i;
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wb_we_o <= wren_i;
|
wb_we_o <= wren_i;
|
data_o <= wb_dat_i;
|
end if;
|
|
if (wb_ack_i = '1') then
|
|
wb_rdata <= wb_dat_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process buffer_stages_two;
|
end process buffer_stages_two;
|
end generate;
|
end generate;
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|
|
