| Line 1... |
Line 1... |
-- #################################################################################################
|
-- #################################################################################################
|
-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
|
-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # The interface is either unregistered (INTERFACE_REG_STAGES = 0), only outgoing signals are #
|
-- # The interface is either unregistered (INTERFACE_REG_STAGES = 0), only outgoing signals are #
|
-- # registered (INTERFACE_REG_STAGES = 1) or incoming and outgoing signals are registered #
|
-- # registered (INTERFACE_REG_STAGES = 1) or incoming and outgoing signals are registered #
|
-- # (INTERFACE_REG_STAGES = 2). #
|
-- # (INTERFACE_REG_STAGES = 2). This interface supports classic/standard Wishbone transactions #
|
|
-- # (WB_PIPELINED_MODE = false) and also pipelined transactions for improved timing #
|
|
-- # (WB_PIPELINED_MODE = true). #
|
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
|
-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
|
-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
|
-- # loader or the internal instruction or data memories (if implemented), are delegated via this #
|
-- # loader or the internal instruction or data memories (if implemented), are delegated via this #
|
-- # Wishbone gateway to the external bus interface. #
|
-- # Wishbone gateway to the external bus interface. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
| Line 48... |
Line 50... |
use neorv32.neorv32_package.all;
|
use neorv32.neorv32_package.all;
|
|
|
entity neorv32_wishbone is
|
entity neorv32_wishbone is
|
generic (
|
generic (
|
INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
|
|
WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
|
-- Internal instruction memory --
|
-- Internal instruction memory --
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
|
-- Internal data memory --
|
-- Internal data memory --
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
MEM_INT_DMEM_USE : boolean := true; -- implement processor-internal data memory
|
| Line 93... |
Line 96... |
signal wb_access : std_ulogic;
|
signal wb_access : std_ulogic;
|
signal wb_access_ff, wb_access_ff_ff : std_ulogic;
|
signal wb_access_ff, wb_access_ff_ff : std_ulogic;
|
signal rb_en : std_ulogic;
|
signal rb_en : std_ulogic;
|
|
|
-- bus arbiter --
|
-- bus arbiter --
|
|
signal wb_we_ff : std_ulogic;
|
signal wb_stb_ff0 : std_ulogic;
|
signal wb_stb_ff0 : std_ulogic;
|
signal wb_stb_ff1 : std_ulogic;
|
signal wb_stb_ff1 : std_ulogic;
|
signal wb_cyc_ff : std_ulogic;
|
signal wb_cyc_ff : std_ulogic;
|
signal wb_ack_ff : std_ulogic;
|
signal wb_ack_ff : std_ulogic;
|
signal wb_err_ff : std_ulogic;
|
signal wb_err_ff : std_ulogic;
|
|
|
|
-- wishbone mode: standard / pipelined --
|
|
signal stb_int_std : std_ulogic;
|
|
signal stb_int_pipe : std_ulogic;
|
|
|
-- data read-back --
|
-- data read-back --
|
signal wb_rdata : std_ulogic_vector(31 downto 0);
|
signal wb_rdata : std_ulogic_vector(31 downto 0);
|
|
|
begin
|
begin
|
|
|
| Line 113... |
Line 121... |
|
|
|
|
-- Access Control -------------------------------------------------------------------------
|
-- Access Control -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- access to internal IMEM or DMEM? --
|
-- access to internal IMEM or DMEM? --
|
int_imem_acc <= '1' when (addr_i >= imem_base_c) and (addr_i < std_ulogic_vector(unsigned(imem_base_c) + MEM_INT_IMEM_SIZE)) else '0';
|
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) else '0';
|
int_dmem_acc <= '1' when (addr_i >= dmem_base_c) and (addr_i < std_ulogic_vector(unsigned(dmem_base_c) + MEM_INT_DMEM_SIZE)) else '0';
|
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) else '0';
|
int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
|
int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
|
int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
|
int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
|
|
|
|
-- access to internal BOOTROM or IO devices? --
|
int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
|
int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
|
|
--int_boot_acc <= '1' when (addr_i(31 downto index_size_f(2*boot_rom_max_size_c)) = boot_rom_base_c(31 downto index_size_f(2*boot_rom_max_size_c))) else '0'; -- this also covers access to the IO space
|
--int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
|
--int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
|
|
|
-- actual external bus access? --
|
-- actual external bus access? --
|
wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc) and (wren_i or rden_i);
|
wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc) and (wren_i or rden_i);
|
|
|
| Line 129... |
Line 140... |
-- Bus Arbiter -----------------------------------------------------------------------------
|
-- Bus Arbiter -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
bus_arbiter: process(rstn_i, clk_i)
|
bus_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
|
wb_we_ff <= '0';
|
wb_cyc_ff <= '0';
|
wb_cyc_ff <= '0';
|
wb_stb_ff1 <= '0';
|
wb_stb_ff1 <= '0';
|
wb_stb_ff0 <= '0';
|
wb_stb_ff0 <= '0';
|
wb_ack_ff <= '0';
|
wb_ack_ff <= '0';
|
wb_err_ff <= '0';
|
wb_err_ff <= '0';
|
wb_access_ff <= '0';
|
wb_access_ff <= '0';
|
wb_access_ff_ff <= '0';
|
wb_access_ff_ff <= '0';
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
|
-- read/write --
|
|
wb_we_ff <= (wb_we_ff or wren_i) and wb_access and (not wb_ack_i) and (not wb_err_i) and (not cancel_i);
|
-- bus cycle --
|
-- bus cycle --
|
if (INTERFACE_REG_STAGES = 0) then
|
if (INTERFACE_REG_STAGES = 0) then
|
wb_cyc_ff <= '0'; -- unused
|
wb_cyc_ff <= '0'; -- unused
|
else
|
else
|
wb_cyc_ff <= (wb_cyc_ff or wb_access) and (not wb_ack_i) and (not wb_err_i) and (not cancel_i);
|
wb_cyc_ff <= (wb_cyc_ff or wb_access) and (not wb_ack_i) and (not wb_err_i) and (not cancel_i);
|
| Line 160... |
Line 174... |
wb_access_ff <= '0';
|
wb_access_ff <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process bus_arbiter;
|
end process bus_arbiter;
|
|
|
-- bus cycle --
|
-- valid bus cycle --
|
wb_cyc_o <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff;
|
wb_cyc_o <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff;
|
|
|
-- bus_strobe: rising edge detector --
|
-- bus strobe --
|
wb_stb_o <= (wb_access and (not wb_stb_ff0)) when (INTERFACE_REG_STAGES = 0) else (wb_stb_ff0 and (not wb_stb_ff1));
|
stb_int_std <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff; -- same as wb_cyc
|
|
stb_int_pipe <= (wb_access and (not wb_stb_ff0)) when (INTERFACE_REG_STAGES = 0) else (wb_stb_ff0 and (not wb_stb_ff1)); -- wb_access rising edge detector
|
|
--
|
|
wb_stb_o <= stb_int_std when (WB_PIPELINED_MODE = false) else stb_int_pipe; -- standard or pipelined mode
|
|
|
-- cpu ack --
|
-- cpu ack --
|
ack_o <= wb_ack_ff when (INTERFACE_REG_STAGES = 2) else wb_ack_i;
|
ack_o <= wb_ack_ff when (INTERFACE_REG_STAGES = 2) else wb_ack_i;
|
|
|
-- cpu err --
|
-- cpu err --
|
| Line 185... |
Line 202... |
if (INTERFACE_REG_STAGES = 0) generate -- 0 register levels: direct connection
|
if (INTERFACE_REG_STAGES = 0) generate -- 0 register levels: direct connection
|
wb_rdata <= wb_dat_i;
|
wb_rdata <= wb_dat_i;
|
wb_adr_o <= addr_i;
|
wb_adr_o <= addr_i;
|
wb_dat_o <= data_i;
|
wb_dat_o <= data_i;
|
wb_sel_o <= ben_i;
|
wb_sel_o <= ben_i;
|
wb_we_o <= wren_i;
|
wb_we_o <= wren_i or wb_we_ff;
|
end generate;
|
end generate;
|
|
|
interface_reg_level_one:
|
interface_reg_level_one:
|
if (INTERFACE_REG_STAGES = 1) generate -- 1 register levels: buffer outgoing signals
|
if (INTERFACE_REG_STAGES = 1) generate -- 1 register levels: buffer outgoing signals
|
buffer_stages_one: process(clk_i)
|
buffer_stages_one: process(clk_i)
|
| Line 197... |
Line 214... |
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (wb_cyc_ff = '0') then
|
if (wb_cyc_ff = '0') then
|
wb_adr_o <= addr_i;
|
wb_adr_o <= addr_i;
|
wb_dat_o <= data_i;
|
wb_dat_o <= data_i;
|
wb_sel_o <= ben_i;
|
wb_sel_o <= ben_i;
|
wb_we_o <= wren_i;
|
wb_we_o <= wren_i or wb_we_ff;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process buffer_stages_one;
|
end process buffer_stages_one;
|
wb_rdata <= wb_dat_i;
|
wb_rdata <= wb_dat_i;
|
end generate;
|
end generate;
|
| Line 213... |
Line 230... |
if rising_edge(clk_i) then
|
if rising_edge(clk_i) then
|
if (wb_cyc_ff = '0') then
|
if (wb_cyc_ff = '0') then
|
wb_adr_o <= addr_i;
|
wb_adr_o <= addr_i;
|
wb_dat_o <= data_i;
|
wb_dat_o <= data_i;
|
wb_sel_o <= ben_i;
|
wb_sel_o <= ben_i;
|
wb_we_o <= wren_i;
|
wb_we_o <= wren_i or wb_we_ff;
|
end if;
|
end if;
|
if (wb_ack_i = '1') then
|
if (wb_ack_i = '1') then
|
wb_rdata <= wb_dat_i;
|
wb_rdata <= wb_dat_i;
|
end if;
|
end if;
|
end if;
|
end if;
|
