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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The interface is either unregistered (INTERFACE_REG_STAGES = 0), only outgoing signals are #
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-- # The interface provides registers for all outgoing signals. If the host cancels a running #
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-- # registered (INTERFACE_REG_STAGES = 1) or incoming and outgoing signals are registered #
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-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK to transfer. #
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-- # (INTERFACE_REG_STAGES = 2). This interface supports classic/standard Wishbone transactions #
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-- # (WB_PIPELINED_MODE = false) and also pipelined transactions for improved timing #
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-- # (WB_PIPELINED_MODE = true). #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
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-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
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-- # loader or the internal instruction or data memories (if implemented), are delegated via this #
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-- # loader or the internal instruction or data memories (if implemented), are delegated via this #
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-- # Wishbone gateway to the external bus interface. #
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-- # Wishbone gateway to the external bus interface. #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_wishbone is
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entity neorv32_wishbone is
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generic (
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generic (
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INTERFACE_REG_STAGES : natural := 2; -- number of interface register stages (0,1,2)
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WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
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-- Internal instruction memory --
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-- Internal instruction memory --
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_USE : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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-- Internal data memory --
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-- Internal data memory --
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);
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);
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end neorv32_wishbone;
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end neorv32_wishbone;
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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-- constants --
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constant wb_timeout_c : natural := bus_timeout_c/2;
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-- access control --
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-- access control --
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signal int_imem_acc, int_imem_acc_real : std_ulogic;
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signal int_imem_acc, int_imem_acc_real : std_ulogic;
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signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal wb_access : std_ulogic;
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signal wb_access : std_ulogic;
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signal wb_access_ff, wb_access_ff_ff : std_ulogic;
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signal rb_en : std_ulogic;
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-- bus arbiter --
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-- bus arbiter
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signal wb_we_ff : std_ulogic;
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type ctrl_state_t is (IDLE, BUSY, CANCELED);
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signal wb_stb_ff0 : std_ulogic;
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type ctrl_t is record
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signal wb_stb_ff1 : std_ulogic;
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state : ctrl_state_t;
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signal wb_cyc_ff : std_ulogic;
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state_prev : ctrl_state_t;
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signal wb_ack_ff : std_ulogic;
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we : std_ulogic;
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signal wb_err_ff : std_ulogic;
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rd_req : std_ulogic;
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wr_req : std_ulogic;
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-- wishbone mode: standard / pipelined --
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adr : std_ulogic_vector(31 downto 0);
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signal stb_int_std : std_ulogic;
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wdat : std_ulogic_vector(31 downto 0);
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signal stb_int_pipe : std_ulogic;
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rdat : std_ulogic_vector(31 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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ack : std_ulogic;
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err : std_ulogic;
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timeout : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0);
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end record;
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signal ctrl : ctrl_t;
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-- data read-back --
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signal stb_int, cyc_int : std_ulogic;
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signal wb_rdata : std_ulogic_vector(31 downto 0);
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begin
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begin
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-- Sanity Check ---------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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assert (INTERFACE_REG_STAGES <= 2) report "NEORV32 CONFIG ERROR! Number of external memory interface buffer stages must be 0, 1 or 2." severity error;
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assert not (bus_timeout_c <= 15) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (bus_timeout_c) should be >16 for interfacing external modules." severity error;
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assert (INTERFACE_REG_STAGES /= 0) report "NEORV32 CONFIG WARNING! External memory interface without register stages is still experimental for peripherals with more than 1 cycle latency." severity warning;
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- access to internal IMEM or DMEM? --
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-- access to internal IMEM or DMEM? --
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int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
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int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
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--int_boot_acc <= '1' when (addr_i(31 downto index_size_f(2*boot_rom_max_size_c)) = boot_rom_base_c(31 downto index_size_f(2*boot_rom_max_size_c))) else '0'; -- this also covers access to the IO space
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--int_boot_acc <= '1' when (addr_i(31 downto index_size_f(2*boot_rom_max_size_c)) = boot_rom_base_c(31 downto index_size_f(2*boot_rom_max_size_c))) else '0'; -- this also covers access to the IO space
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--int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
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--int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
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-- actual external bus access? --
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-- actual external bus access? --
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wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc) and (wren_i or rden_i);
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wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc);
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- Bus Arbiter -----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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bus_arbiter: process(rstn_i, clk_i)
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bus_arbiter: process(rstn_i, clk_i)
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begin
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begin
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if (rstn_i = '0') then
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if (rstn_i = '0') then
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wb_we_ff <= '0';
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ctrl.state <= IDLE;
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wb_cyc_ff <= '0';
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ctrl.state_prev <= IDLE;
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wb_stb_ff1 <= '0';
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ctrl.we <= '0';
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wb_stb_ff0 <= '0';
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ctrl.rd_req <= '0';
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wb_ack_ff <= '0';
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ctrl.wr_req <= '0';
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wb_err_ff <= '0';
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ctrl.adr <= (others => '0');
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wb_access_ff <= '0';
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ctrl.wdat <= (others => '0');
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wb_access_ff_ff <= '0';
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ctrl.rdat <= (others => '0');
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ctrl.sel <= (others => '0');
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ctrl.timeout <= (others => '0');
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ctrl.ack <= '0';
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ctrl.err <= '0';
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elsif rising_edge(clk_i) then
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elsif rising_edge(clk_i) then
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-- read/write --
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-- defaults --
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wb_we_ff <= (wb_we_ff or wren_i) and wb_access and (not wb_ack_i) and (not wb_err_i) and (not cancel_i);
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ctrl.state_prev <= ctrl.state;
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-- bus cycle --
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ctrl.rdat <= (others => '0');
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if (INTERFACE_REG_STAGES = 0) then
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ctrl.ack <= '0';
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wb_cyc_ff <= '0'; -- unused
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ctrl.err <= '0';
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else
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ctrl.timeout <= std_ulogic_vector(to_unsigned(wb_timeout_c, index_size_f(wb_timeout_c)));
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wb_cyc_ff <= (wb_cyc_ff or wb_access) and (not wb_ack_i) and (not wb_err_i) and (not cancel_i);
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end if;
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-- state machine --
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-- bus strobe --
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case ctrl.state is
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wb_stb_ff1 <= wb_stb_ff0;
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wb_stb_ff0 <= wb_access;
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when IDLE => -- waiting for host request
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-- bus ack --
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-- ------------------------------------------------------------
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wb_ack_ff <= wb_ack_i;
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ctrl.rd_req <= '0';
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-- bus err --
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ctrl.wr_req <= '0';
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wb_err_ff <= wb_err_i;
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-- buffer all outgoing signals --
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-- access still active? --
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ctrl.we <= wren_i;
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wb_access_ff_ff <= wb_access_ff;
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ctrl.adr <= addr_i;
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if (wb_access = '1') then
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ctrl.wdat <= data_i;
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wb_access_ff <= '1';
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ctrl.sel <= ben_i;
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elsif ((wb_ack_i or wb_err_i or cancel_i) = '1') then
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-- valid read/write access --
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wb_access_ff <= '0';
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if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
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end if;
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ctrl.state <= BUSY;
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end if;
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when BUSY => -- transfer in progress
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-- ------------------------------------------------------------
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ctrl.rdat <= wb_dat_i;
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if (cancel_i = '1') then -- transfer canceled by host
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ctrl.state <= CANCELED;
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elsif (wb_err_i = '1') then -- abnormal bus termination
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ctrl.err <= '1';
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ctrl.state <= CANCELED;
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elsif (wb_ack_i = '1') then -- normal bus termination
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ctrl.ack <= '1';
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ctrl.state <= IDLE;
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end if;
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when CANCELED => --
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-- ------------------------------------------------------------
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ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
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ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
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-- wait for bus.peripheral to ACK transfer (as "aborted" but still somehow "completed")
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-- or wait for a timeout and force termination
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ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
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if (wb_ack_i = '1') or (or_all_f(ctrl.timeout) = '0') then
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ctrl.state <= IDLE;
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end if;
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when others => -- undefined
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-- ------------------------------------------------------------
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ctrl.state <= IDLE;
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end case;
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end if;
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end if;
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end process bus_arbiter;
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end process bus_arbiter;
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-- valid bus cycle --
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wb_cyc_o <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff;
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-- bus strobe --
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stb_int_std <= wb_access when (INTERFACE_REG_STAGES = 0) else wb_cyc_ff; -- same as wb_cyc
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stb_int_pipe <= (wb_access and (not wb_stb_ff0)) when (INTERFACE_REG_STAGES = 0) else (wb_stb_ff0 and (not wb_stb_ff1)); -- wb_access rising edge detector
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--
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wb_stb_o <= stb_int_std when (WB_PIPELINED_MODE = false) else stb_int_pipe; -- standard or pipelined mode
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-- cpu ack --
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ack_o <= wb_ack_ff when (INTERFACE_REG_STAGES = 2) else wb_ack_i;
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-- cpu err --
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-- host access --
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err_o <= wb_err_ff when (INTERFACE_REG_STAGES = 2) else wb_err_i;
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data_o <= ctrl.rdat;
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ack_o <= ctrl.ack;
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-- cpu read-data --
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err_o <= ctrl.err;
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rb_en <= wb_access_ff_ff when (INTERFACE_REG_STAGES = 2) else wb_access_ff;
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data_o <= wb_rdata when (rb_en = '1') else (others => '0');
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-- wishbone interface --
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wb_adr_o <= ctrl.adr;
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wb_dat_o <= ctrl.wdat;
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wb_we_o <= ctrl.we;
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wb_sel_o <= ctrl.sel;
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wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
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wb_cyc_o <= cyc_int;
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-- Bus Buffer -----------------------------------------------------------------------------
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stb_int <= '1' when ((ctrl.state = BUSY) and (ctrl.state_prev = IDLE)) else '0';
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-- -------------------------------------------------------------------------------------------
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cyc_int <= '0' when (ctrl.state = IDLE) else '1';
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interface_reg_level_zero:
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if (INTERFACE_REG_STAGES = 0) generate -- 0 register levels: direct connection
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wb_rdata <= wb_dat_i;
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wb_adr_o <= addr_i;
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wb_dat_o <= data_i;
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wb_sel_o <= ben_i;
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wb_we_o <= wren_i or wb_we_ff;
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end generate;
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interface_reg_level_one:
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if (INTERFACE_REG_STAGES = 1) generate -- 1 register levels: buffer outgoing signals
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buffer_stages_one: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (wb_cyc_ff = '0') then
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wb_adr_o <= addr_i;
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wb_dat_o <= data_i;
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wb_sel_o <= ben_i;
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wb_we_o <= wren_i or wb_we_ff;
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end if;
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end if;
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end process buffer_stages_one;
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wb_rdata <= wb_dat_i;
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end generate;
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interface_reg_level_two:
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if (INTERFACE_REG_STAGES = 2) generate -- 2 register levels: buffer incoming and outgoing signals
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buffer_stages_two: process(clk_i)
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begin
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if rising_edge(clk_i) then
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if (wb_cyc_ff = '0') then
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wb_adr_o <= addr_i;
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wb_dat_o <= data_i;
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wb_sel_o <= ben_i;
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wb_we_o <= wren_i or wb_we_ff;
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end if;
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if (wb_ack_i = '1') then
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wb_rdata <= wb_dat_i;
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end if;
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end if;
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end process buffer_stages_two;
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end generate;
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end neorv32_wishbone_rtl;
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end neorv32_wishbone_rtl;
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No newline at end of file
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No newline at end of file
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