| Line 1... |
Line 1... |
-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # << NEORV32 - External Bus Interface (WISHBONE) >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # The interface provides registers for all outgoing signals. If the host cancels a running #
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-- # The interface provides registers for all outgoing signals. If the host cancels a running #
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-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK to transfer. #
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-- # transfer, the Wishbone arbiter still waits some time for the bus system to ACK the transfer #
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-- # before the arbiter forces termination. #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # All bus accesses from the CPU, which do not target the internal IO region, the internal boot- #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # loader or the internal instruction or data memories (if implemented), are delegated via this #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # Wishbone gateway to the external bus interface. #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # All bus accesses from the CPU, which do not target the internal IO region / the internal #
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-- # bootlloader / the internal instruction or data memories (if implemented), are delegated via #
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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
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-- # latency of up to neorv32_package.vhd:bus_timeout_c - 2 cycles. #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - #
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
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-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false) #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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| Line 70... |
Line 75... |
wren_i : in std_ulogic; -- write enable
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wren_i : in std_ulogic; -- write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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ben_i : in std_ulogic_vector(03 downto 0); -- byte write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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cancel_i : in std_ulogic; -- cancel current bus transaction
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cancel_i : in std_ulogic; -- cancel current bus transaction
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lock_i : in std_ulogic; -- locked/exclusive bus access
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ack_o : out std_ulogic; -- transfer acknowledge
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ack_o : out std_ulogic; -- transfer acknowledge
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err_o : out std_ulogic; -- transfer error
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err_o : out std_ulogic; -- transfer error
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priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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priv_i : in std_ulogic_vector(1 downto 0); -- current CPU privilege level
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-- wishbone interface --
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-- wishbone interface --
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wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
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wb_tag_o : out std_ulogic_vector(2 downto 0); -- tag
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| Line 82... |
Line 88... |
wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
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wb_we_o : out std_ulogic; -- read/write
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wb_we_o : out std_ulogic; -- read/write
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
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wb_stb_o : out std_ulogic; -- strobe
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wb_stb_o : out std_ulogic; -- strobe
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_cyc_o : out std_ulogic; -- valid cycle
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wb_lock_o : out std_ulogic; -- locked/exclusive bus access
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_ack_i : in std_ulogic; -- transfer acknowledge
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wb_err_i : in std_ulogic -- transfer error
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wb_err_i : in std_ulogic -- transfer error
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);
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);
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end neorv32_wishbone;
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end neorv32_wishbone;
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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architecture neorv32_wishbone_rtl of neorv32_wishbone is
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-- constants --
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-- constants --
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constant wb_timeout_c : natural := bus_timeout_c/2;
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constant xbus_timeout_c : natural := bus_timeout_c/4;
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-- access control --
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-- access control --
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signal int_imem_acc, int_imem_acc_real : std_ulogic;
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signal int_imem_acc : std_ulogic;
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signal int_dmem_acc, int_dmem_acc_real : std_ulogic;
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signal int_dmem_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal int_boot_acc : std_ulogic;
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signal wb_access : std_ulogic;
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signal xbus_access : std_ulogic;
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-- bus arbiter
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-- bus arbiter
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type ctrl_state_t is (IDLE, BUSY, CANCELED, RESYNC);
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type ctrl_state_t is (IDLE, BUSY, CANCELED, RESYNC);
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type ctrl_t is record
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type ctrl_t is record
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state : ctrl_state_t;
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state : ctrl_state_t;
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state_prev : ctrl_state_t;
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we : std_ulogic;
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we : std_ulogic;
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rd_req : std_ulogic;
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rd_req : std_ulogic;
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wr_req : std_ulogic;
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wr_req : std_ulogic;
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adr : std_ulogic_vector(31 downto 0);
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adr : std_ulogic_vector(31 downto 0);
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wdat : std_ulogic_vector(31 downto 0);
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wdat : std_ulogic_vector(31 downto 0);
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rdat : std_ulogic_vector(31 downto 0);
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rdat : std_ulogic_vector(31 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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ack : std_ulogic;
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ack : std_ulogic;
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err : std_ulogic;
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err : std_ulogic;
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timeout : std_ulogic_vector(index_size_f(wb_timeout_c)-1 downto 0);
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timeout : std_ulogic_vector(index_size_f(xbus_timeout_c)-1 downto 0);
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src : std_ulogic;
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src : std_ulogic;
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lock : std_ulogic;
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priv : std_ulogic_vector(1 downto 0);
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priv : std_ulogic_vector(1 downto 0);
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end record;
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end record;
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signal ctrl : ctrl_t;
|
signal ctrl : ctrl_t;
|
signal stb_int : std_ulogic;
|
signal stb_int : std_ulogic;
|
signal cyc_int : std_ulogic;
|
signal cyc_int : std_ulogic;
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|
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begin
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begin
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|
|
-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
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assert not (bus_timeout_c <= 15) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (bus_timeout_c) should be >16 for interfacing external modules." severity error;
|
-- max bus timeout latency lower than recommended --
|
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assert not (bus_timeout_c <= 32) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (neorv32_package.vhd:bus_timeout_c) should be >32 when using external bus interface." severity error;
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-- external memory iterface protocol + max timeout latency notifier (warning) --
|
|
assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning;
|
|
assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using PIEPLINED Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning;
|
|
|
|
|
-- Access Control -------------------------------------------------------------------------
|
-- Access Control -------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- access to internal IMEM or DMEM? --
|
-- access to processor-internal IMEM or DMEM? --
|
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) else '0';
|
int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_USE = true) else '0';
|
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) else '0';
|
int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_USE = true) else '0';
|
int_imem_acc_real <= int_imem_acc when (MEM_INT_IMEM_USE = true) else '0';
|
-- access to processor-internal BOOTROM or IO devices? --
|
int_dmem_acc_real <= int_dmem_acc when (MEM_INT_DMEM_USE = true) else '0';
|
int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
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|
|
-- access to internal BOOTROM or IO devices? --
|
|
int_boot_acc <= '1' when (addr_i >= boot_rom_base_c) else '0'; -- this also covers access to the IO space
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|
--int_boot_acc <= '1' when (addr_i(31 downto index_size_f(2*boot_rom_max_size_c)) = boot_rom_base_c(31 downto index_size_f(2*boot_rom_max_size_c))) else '0'; -- this also covers access to the IO space
|
|
--int_io_acc <= '1' when (addr_i >= io_base_c) else '0';
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|
|
|
-- actual external bus access? --
|
-- actual external bus access? --
|
wb_access <= (not int_imem_acc_real) and (not int_dmem_acc_real) and (not int_boot_acc);
|
xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc);
|
|
|
-- Bus Arbiter -----------------------------------------------------------------------------
|
-- Bus Arbiter -----------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
bus_arbiter: process(rstn_i, clk_i)
|
bus_arbiter: process(rstn_i, clk_i)
|
begin
|
begin
|
if (rstn_i = '0') then
|
if (rstn_i = '0') then
|
ctrl.state <= IDLE;
|
ctrl.state <= IDLE;
|
ctrl.state_prev <= IDLE;
|
|
ctrl.we <= '0';
|
ctrl.we <= '0';
|
ctrl.rd_req <= '0';
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ctrl.rd_req <= '0';
|
ctrl.wr_req <= '0';
|
ctrl.wr_req <= '0';
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ctrl.adr <= (others => '0');
|
ctrl.adr <= (others => '0');
|
ctrl.wdat <= (others => '0');
|
ctrl.wdat <= (others => '0');
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| Line 161... |
Line 165... |
ctrl.sel <= (others => '0');
|
ctrl.sel <= (others => '0');
|
ctrl.timeout <= (others => '0');
|
ctrl.timeout <= (others => '0');
|
ctrl.ack <= '0';
|
ctrl.ack <= '0';
|
ctrl.err <= '0';
|
ctrl.err <= '0';
|
ctrl.src <= '0';
|
ctrl.src <= '0';
|
|
ctrl.lock <= '0';
|
ctrl.priv <= "00";
|
ctrl.priv <= "00";
|
elsif rising_edge(clk_i) then
|
elsif rising_edge(clk_i) then
|
-- defaults --
|
-- defaults --
|
ctrl.state_prev <= ctrl.state;
|
|
ctrl.rdat <= (others => '0');
|
ctrl.rdat <= (others => '0');
|
ctrl.ack <= '0';
|
ctrl.ack <= '0';
|
ctrl.err <= '0';
|
ctrl.err <= '0';
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(wb_timeout_c, index_size_f(wb_timeout_c)));
|
ctrl.timeout <= std_ulogic_vector(to_unsigned(xbus_timeout_c, index_size_f(xbus_timeout_c)));
|
|
|
-- state machine --
|
-- state machine --
|
case ctrl.state is
|
case ctrl.state is
|
|
|
when IDLE => -- waiting for host request
|
when IDLE => -- waiting for host request
|
| Line 183... |
Line 187... |
ctrl.we <= wren_i;
|
ctrl.we <= wren_i;
|
ctrl.adr <= addr_i;
|
ctrl.adr <= addr_i;
|
ctrl.wdat <= data_i;
|
ctrl.wdat <= data_i;
|
ctrl.sel <= ben_i;
|
ctrl.sel <= ben_i;
|
ctrl.src <= src_i;
|
ctrl.src <= src_i;
|
|
ctrl.lock <= lock_i;
|
ctrl.priv <= priv_i;
|
ctrl.priv <= priv_i;
|
-- valid read/write access --
|
-- valid new or buffered read/write request --
|
if ((wb_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
|
if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
|
ctrl.state <= BUSY;
|
ctrl.state <= BUSY;
|
end if;
|
end if;
|
|
|
when BUSY => -- transfer in progress
|
when BUSY => -- transfer in progress
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
| Line 241... |
Line 246... |
|
|
wb_adr_o <= ctrl.adr;
|
wb_adr_o <= ctrl.adr;
|
wb_dat_o <= ctrl.wdat;
|
wb_dat_o <= ctrl.wdat;
|
wb_we_o <= ctrl.we;
|
wb_we_o <= ctrl.we;
|
wb_sel_o <= ctrl.sel;
|
wb_sel_o <= ctrl.sel;
|
|
wb_lock_o <= ctrl.lock;
|
wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
|
wb_stb_o <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
|
wb_cyc_o <= cyc_int;
|
wb_cyc_o <= cyc_int;
|
|
|
stb_int <= '1' when ((ctrl.state = BUSY) and (ctrl.state_prev = IDLE)) else '0';
|
stb_int <= '1' when (ctrl.state = BUSY) else '0';
|
cyc_int <= '0' when ((ctrl.state = IDLE) or (ctrl.state = RESYNC)) else '1';
|
cyc_int <= '0' when (ctrl.state = IDLE) or (ctrl.state = RESYNC) else '1';
|
|
|
|
|
end neorv32_wishbone_rtl;
|
end neorv32_wishbone_rtl;
|
|
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No newline at end of file
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No newline at end of file
|
