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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_wishbone.vhd] - Diff between revs 39 and 40

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Rev 39 Rev 40
Line 134... Line 134...
  -- Sanity Checks --------------------------------------------------------------------------
  -- Sanity Checks --------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- max bus timeout latency lower than recommended --
  -- max bus timeout latency lower than recommended --
  assert not (bus_timeout_c <= 32) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (neorv32_package.vhd:bus_timeout_c) should be >32 when using external bus interface." severity error;
  assert not (bus_timeout_c <= 32) report "NEORV32 PROCESSOR CONFIG ERROR: Bus timeout (neorv32_package.vhd:bus_timeout_c) should be >32 when using external bus interface." severity error;
  -- external memory iterface protocol + max timeout latency notifier (warning) --
  -- external memory iterface protocol + max timeout latency notifier (warning) --
  assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning;
  assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity note;
  assert not (wb_pipe_mode_c =  true) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using PIEPLINED Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning;
  assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG WARNING! Implementing external memory interface using PIEPLINED Wishbone protocol with max latency = " & integer'image(bus_timeout_c) & " cycles." severity warning;
 
  -- endianness --
 
  assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note;
 
  assert not (xbus_big_endian_c = true)  report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note;
 
 
 
 
  -- Access Control -------------------------------------------------------------------------
  -- Access Control -------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- -------------------------------------------------------------------------------------------
  -- access to processor-internal IMEM or DMEM? --
  -- access to processor-internal IMEM or DMEM? --
Line 184... Line 187...
          ctrl.rd_req <= '0';
          ctrl.rd_req <= '0';
          ctrl.wr_req <= '0';
          ctrl.wr_req <= '0';
          -- buffer all outgoing signals --
          -- buffer all outgoing signals --
          ctrl.we   <= wren_i;
          ctrl.we   <= wren_i;
          ctrl.adr  <= addr_i;
          ctrl.adr  <= addr_i;
 
          if (xbus_big_endian_c = true) then -- endianness conversion
          ctrl.wdat <= data_i;
          ctrl.wdat <= data_i;
          ctrl.sel  <= ben_i;
          ctrl.sel  <= ben_i;
 
          else
 
            ctrl.wdat <= bswap32_f(data_i);
 
            ctrl.sel  <= bit_rev_f(ben_i);
 
          end if;
          ctrl.src  <= src_i;
          ctrl.src  <= src_i;
          ctrl.lock <= lock_i;
          ctrl.lock <= lock_i;
          ctrl.priv <= priv_i;
          ctrl.priv <= priv_i;
          -- valid new or buffered read/write request --
          -- valid new or buffered read/write request --
          if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
          if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req)) = '1') then
Line 233... Line 241...
      end case;
      end case;
    end if;
    end if;
  end process bus_arbiter;
  end process bus_arbiter;
 
 
  -- host access --
  -- host access --
  data_o <= ctrl.rdat;
  data_o <= ctrl.rdat when (xbus_big_endian_c = true) else bswap32_f(ctrl.rdat); -- endianness conversion
  ack_o  <= ctrl.ack;
  ack_o  <= ctrl.ack;
  err_o  <= ctrl.err;
  err_o  <= ctrl.err;
 
 
  -- wishbone interface --
  -- wishbone interface --
  wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
  wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode

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