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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
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-- # latency of up to BUS_TIMEOUT - 1 cycles. #
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-- # latency of up to BUS_TIMEOUT - 1 cycles. #
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-- # #
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-- # #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space). #
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-- # #
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-- # The interface uses registers for ALL OUTGOING AND FOR ALL INCOMING signals. Hence, an access #
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-- # latency of (at least) 2 cycles is added. #
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-- # #
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-- # This interface supports classic/standard Wishbone transactions (pkg.wb_pipe_mode_c = false) #
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-- # and also pipelined transactions (pkg.wb_pipe_mode_c = true). #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2021, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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Line 48... |
use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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entity neorv32_wishbone is
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entity neorv32_wishbone is
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generic (
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generic (
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-- Internal instruction memory --
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-- Internal instruction memory --
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MEM_INT_IMEM_EN : boolean := true; -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN : boolean; -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE : natural; -- size of processor-internal instruction memory in bytes
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-- Internal data memory --
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-- Internal data memory --
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MEM_INT_DMEM_EN : boolean := true; -- implement processor-internal data memory
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MEM_INT_DMEM_EN : boolean; -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE : natural; -- size of processor-internal data memory in bytes
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-- Bus Timeout --
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-- Interface Configuration --
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BUS_TIMEOUT : natural := 63 -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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BUS_TIMEOUT : natural; -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
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PIPE_MODE : boolean; -- protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
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BIG_ENDIAN : boolean; -- byte order: true=big-endian, false=little-endian
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ASYNC_RX : boolean -- use register buffer for RX data when false
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);
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);
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port (
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port (
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-- global control --
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-- global control --
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clk_i : in std_ulogic; -- global clock line
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clk_i : in std_ulogic; -- global clock line
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rstn_i : in std_ulogic; -- global reset line, low-active
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rstn_i : in std_ulogic; -- global reset line, low-active
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| Line 134... |
Line 131... |
begin
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begin
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-- Sanity Checks --------------------------------------------------------------------------
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-- Sanity Checks --------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- protocol --
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-- protocol --
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assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing STANDARD Wishbone protocol." severity note;
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assert not (PIPE_MODE = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing STANDARD Wishbone protocol." severity note;
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assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing PIEPLINED Wishbone protocol." severity note;
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assert not (PIPE_MODE = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing PIEPLINED Wishbone protocol." severity note;
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-- bus timeout --
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-- bus timeout --
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assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing auto-timeout (" & integer'image(BUS_TIMEOUT) & " cycles)." severity note;
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assert not (BUS_TIMEOUT /= 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing auto-timeout (" & integer'image(BUS_TIMEOUT) & " cycles)." severity note;
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assert not (BUS_TIMEOUT = 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing no auto-timeout (can cause permanent CPU stall!)." severity note;
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assert not (BUS_TIMEOUT = 0) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing no auto-timeout (can cause permanent CPU stall!)." severity note;
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-- endianness --
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-- endianness --
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assert not (wb_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing LITTLE-endian byte order." severity note;
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assert not (BIG_ENDIAN = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing LITTLE-endian byte order." severity note;
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assert not (wb_big_endian_c = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing BIG-endian byte." severity note;
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assert not (BIG_ENDIAN = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing BIG-endian byte." severity note;
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-- async RC --
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-- async RX --
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assert not (wb_rx_buffer_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing ASYNC RX path." severity note;
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assert not (ASYNC_RX = false) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing registered RX path." severity note;
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assert not (ASYNC_RX = true) report "NEORV32 PROCESSOR CONFIG NOTE: External Bus Interface - Implementing ASYNC RX path." severity note;
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-- Access Control -------------------------------------------------------------------------
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- access to processor-internal IMEM or DMEM? --
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-- access to processor-internal IMEM or DMEM? --
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when IDLE => -- waiting for host request
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when IDLE => -- waiting for host request
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-- ------------------------------------------------------------
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-- ------------------------------------------------------------
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-- buffer all outgoing signals --
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-- buffer all outgoing signals --
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ctrl.we <= wren_i;
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ctrl.we <= wren_i;
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ctrl.adr <= addr_i;
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ctrl.adr <= addr_i;
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if (wb_big_endian_c = true) then -- big-endian
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if (BIG_ENDIAN = true) then -- big-endian
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ctrl.wdat <= bswap32_f(data_i);
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ctrl.wdat <= bswap32_f(data_i);
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ctrl.sel <= bit_rev_f(ben_i);
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ctrl.sel <= bit_rev_f(ben_i);
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else -- little-endian
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else -- little-endian
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ctrl.wdat <= data_i;
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ctrl.wdat <= data_i;
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ctrl.sel <= ben_i;
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ctrl.sel <= ben_i;
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| Line 234... |
Line 232... |
end process bus_arbiter;
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end process bus_arbiter;
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-- host access --
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-- host access --
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ack_gated <= wb_ack_i when (ctrl.state = BUSY) else '0'; -- CPU ack gate for "async" RX
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ack_gated <= wb_ack_i when (ctrl.state = BUSY) else '0'; -- CPU ack gate for "async" RX
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rdata_gated <= wb_dat_i when (ctrl.state = BUSY) else (others => '0'); -- CPU read data gate for "async" RX
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rdata_gated <= wb_dat_i when (ctrl.state = BUSY) else (others => '0'); -- CPU read data gate for "async" RX
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rdata <= ctrl.rdat when (wb_rx_buffer_c = true) else rdata_gated;
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rdata <= ctrl.rdat when (ASYNC_RX = false) else rdata_gated;
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data_o <= rdata when (wb_big_endian_c = false) else bswap32_f(rdata); -- endianness conversion
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data_o <= rdata when (BIG_ENDIAN = false) else bswap32_f(rdata); -- endianness conversion
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ack_o <= ctrl.ack when (wb_rx_buffer_c = true) else ack_gated;
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ack_o <= ctrl.ack when (ASYNC_RX = false) else ack_gated;
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err_o <= ctrl.err;
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err_o <= ctrl.err;
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-- wishbone interface --
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-- wishbone interface --
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wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
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wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
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wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
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wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
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| Line 251... |
Line 249... |
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wb_adr_o <= ctrl.adr;
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wb_adr_o <= ctrl.adr;
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wb_dat_o <= ctrl.wdat;
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wb_dat_o <= ctrl.wdat;
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wb_we_o <= ctrl.we;
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wb_we_o <= ctrl.we;
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wb_sel_o <= ctrl.sel;
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wb_sel_o <= ctrl.sel;
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wb_stb_o <= stb_int when (wb_pipe_mode_c = true) else cyc_int;
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wb_stb_o <= stb_int when (PIPE_MODE = true) else cyc_int;
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wb_cyc_o <= cyc_int;
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wb_cyc_o <= cyc_int;
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|
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stb_int <= '1' when (ctrl.state = BUSY) else '0';
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stb_int <= '1' when (ctrl.state = BUSY) else '0';
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cyc_int <= '1' when (ctrl.state = BUSY) else '0';
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cyc_int <= '1' when (ctrl.state = BUSY) else '0';
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