| Line 95... |
Line 95... |
XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := (others => '1'); -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
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IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
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IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
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IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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| Line 314... |
Line 318... |
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
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IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
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IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO => IO_UART0_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO => IO_UART1_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
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IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
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IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
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IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled
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IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
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IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
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IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
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IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
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| Line 439... |
Line 447... |
gpio_o <= std_logic_vector(gpio_o_int);
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gpio_o <= std_logic_vector(gpio_o_int);
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gpio_i_int <= std_ulogic_vector(gpio_i);
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gpio_i_int <= std_ulogic_vector(gpio_i);
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uart0_txd_o <= std_logic(uart0_txd_o_int);
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uart0_txd_o <= std_logic(uart0_txd_o_int);
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uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
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uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
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uart0_rts_o <= std_logic(uart0_rts_o_int);
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uart0_cts_i_int <= std_ulogic(uart0_cts_i);
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uart1_txd_o <= std_logic(uart1_txd_o_int);
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uart1_txd_o <= std_logic(uart1_txd_o_int);
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uart1_rxd_i_int <= std_ulogic(uart1_rxd_i);
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uart1_rxd_i_int <= std_ulogic(uart1_rxd_i);
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uart1_rts_o <= std_logic(uart1_rts_o_int);
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uart1_cts_i_int <= std_ulogic(uart1_cts_i);
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spi_sck_o <= std_logic(spi_sck_o_int);
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spi_sck_o <= std_logic(spi_sck_o_int);
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spi_sdo_o <= std_logic(spi_sdo_o_int);
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spi_sdo_o <= std_logic(spi_sdo_o_int);
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spi_sdi_i_int <= std_ulogic(spi_sdi_i);
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spi_sdi_i_int <= std_ulogic(spi_sdi_i);
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spi_csn_o <= std_logic_vector(spi_csn_o_int);
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spi_csn_o <= std_logic_vector(spi_csn_o_int);
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