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Line 105... |
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN : boolean := false; -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_MTIME_EN : boolean := false; -- implement machine system timer (MTIME)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN : boolean := false; -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN : boolean := false; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_SPI_EN : boolean := false; -- implement serial peripheral interface (SPI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_TWI_EN : boolean := false; -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_PWM_NUM_CH : natural := 0; -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_WDT_EN : boolean := false; -- implement watch dog timer (WDT)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN => IO_GPIO_EN,
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IO_GPIO_EN => IO_GPIO_EN,
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IO_MTIME_EN => IO_MTIME_EN,
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IO_MTIME_EN => IO_MTIME_EN,
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IO_UART0_EN => IO_UART0_EN,
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IO_UART0_EN => IO_UART0_EN,
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IO_UART0_RX_FIFO => IO_UART0_RX_FIFO,
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IO_UART0_TX_FIFO => IO_UART0_TX_FIFO,
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IO_UART1_EN => IO_UART1_EN,
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IO_UART1_EN => IO_UART1_EN,
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IO_UART1_RX_FIFO => IO_UART1_RX_FIFO,
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IO_UART1_TX_FIFO => IO_UART1_TX_FIFO,
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IO_SPI_EN => IO_SPI_EN,
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IO_SPI_EN => IO_SPI_EN,
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IO_TWI_EN => IO_TWI_EN,
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IO_TWI_EN => IO_TWI_EN,
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IO_PWM_NUM_CH => IO_PWM_NUM_CH,
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IO_PWM_NUM_CH => IO_PWM_NUM_CH,
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IO_WDT_EN => IO_WDT_EN,
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IO_WDT_EN => IO_WDT_EN,
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IO_TRNG_EN => IO_TRNG_EN,
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IO_TRNG_EN => IO_TRNG_EN,
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Line 397... |
xirq_i => xirq_i,
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xirq_i => xirq_i,
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-- CPU interrupts --
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-- CPU interrupts --
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mtime_irq_i => mtime_irq_i,
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mtime_irq_i => mtime_irq_i,
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msw_irq_i => msw_irq_i,
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msw_irq_i => msw_irq_i,
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mext_irq_i => mext_irq_i);
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mext_irq_i => mext_irq_i
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);
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-- Wishbone to AvalonMM brdige
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-- Wishbone to AvalonMM bridge
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read_o <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0';
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read_o <= '1' when (wb_stb_o = '1' and wb_we_o = '0') else '0';
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write_o <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0';
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write_o <= '1' when (wb_stb_o = '1' and wb_we_o = '1') else '0';
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address_o <= std_logic_vector(wb_adr_o);
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address_o <= std_logic_vector(wb_adr_o);
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writedata_o <= std_logic_vector(wb_dat_o);
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writedata_o <= std_logic_vector(wb_dat_o);
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byteenable_o <= std_logic_vector(wb_sel_o);
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byteenable_o <= std_logic_vector(wb_sel_o);
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