| Line 90... |
Line 90... |
XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
XIRQ_TRIGGER_POLARITY : std_logic_vector(31 downto 0) := x"FFFFFFFF"; -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN : boolean := true; -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_MTIME_EN : boolean := true; -- implement machine system timer (MTIME)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN : boolean := true; -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
|
IO_UART0_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
|
|
IO_UART0_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_UART1_EN : boolean := true; -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
|
IO_UART1_RX_FIFO : natural := 1; -- RX fifo depth, has to be a power of two, min 1
|
|
IO_UART1_TX_FIFO : natural := 1; -- TX fifo depth, has to be a power of two, min 1
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN : boolean := true; -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_TWI_EN : boolean := true; -- implement two-wire interface (TWI)?
|
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_PWM_NUM_CH : natural := 4; -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_WDT_EN : boolean := true; -- implement watch dog timer (WDT)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_TRNG_EN : boolean := false; -- implement true random number generator (TRNG)?
|
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
|
IO_CFS_EN : boolean := false; -- implement custom functions subsystem (CFS)?
|
IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
|
IO_CFS_CONFIG : std_logic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
|
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
|
IO_CFS_IN_SIZE : positive := 32; -- size of CFS input conduit in bits
|
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
|
IO_CFS_OUT_SIZE : positive := 32; -- size of CFS output conduit in bits
|
IO_NEOLED_EN : boolean := true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_EN : boolean := true; -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
|
IO_NEOLED_TX_FIFO : natural := 1 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
);
|
);
|
port (
|
port (
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
-- AXI4-Lite-Compatible Master Interface --
|
-- AXI4-Lite-Compatible Master Interface --
|
-- ------------------------------------------------------------
|
-- ------------------------------------------------------------
|
| Line 315... |
Line 320... |
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
XIRQ_TRIGGER_POLARITY => XIRQ_TRIGGER_POLARITY_INT, -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
|
-- Processor peripherals --
|
-- Processor peripherals --
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_GPIO_EN => IO_GPIO_EN, -- implement general purpose input/output port unit (GPIO)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
IO_MTIME_EN => IO_MTIME_EN, -- implement machine system timer (MTIME)?
|
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
IO_UART0_EN => IO_UART0_EN, -- implement primary universal asynchronous receiver/transmitter (UART0)?
|
|
IO_UART0_RX_FIFO => IO_UART0_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
|
IO_UART0_TX_FIFO => IO_UART0_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1
|
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
IO_UART1_EN => IO_UART1_EN, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
|
|
IO_UART1_RX_FIFO => IO_UART1_RX_FIFO, -- RX fifo depth, has to be a power of two, min 1
|
|
IO_UART1_TX_FIFO => IO_UART1_TX_FIFO, -- TX fifo depth, has to be a power of two, min 1
|
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
|
IO_SPI_EN => IO_SPI_EN, -- implement serial peripheral interface (SPI)?
|
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
IO_TWI_EN => IO_TWI_EN, -- implement two-wire interface (TWI)?
|
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_PWM_NUM_CH => IO_PWM_NUM_CH, -- number of PWM channels to implement (0..60); 0 = disabled
|
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
IO_WDT_EN => IO_WDT_EN, -- implement watch dog timer (WDT)?
|
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
IO_TRNG_EN => IO_TRNG_EN, -- implement true random number generator (TRNG)?
|
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
|
IO_CFS_EN => IO_CFS_EN, -- implement custom functions subsystem (CFS)?
|
IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic
|
IO_CFS_CONFIG => IO_CFS_CONFIG_INT, -- custom CFS configuration generic
|
IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
|
IO_CFS_IN_SIZE => IO_CFS_IN_SIZE, -- size of CFS input conduit in bits
|
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits
|
IO_CFS_OUT_SIZE => IO_CFS_OUT_SIZE, -- size of CFS output conduit in bits
|
IO_NEOLED_EN => IO_NEOLED_EN -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
IO_NEOLED_EN => IO_NEOLED_EN, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
|
|
IO_NEOLED_TX_FIFO => IO_NEOLED_TX_FIFO -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
|
)
|
)
|
port map (
|
port map (
|
-- Global control --
|
-- Global control --
|
clk_i => clk_i_int, -- global clock, rising edge
|
clk_i => clk_i_int, -- global clock, rising edge
|
rstn_i => rstn_i_int, -- global reset, low-active, async
|
rstn_i => rstn_i_int, -- global reset, low-active, async
|
| Line 403... |
Line 413... |
jtag_tdo_o <= std_logic(jtag_tdo_o_int);
|
jtag_tdo_o <= std_logic(jtag_tdo_o_int);
|
jtag_tms_i_int <= std_ulogic(jtag_tms_i);
|
jtag_tms_i_int <= std_ulogic(jtag_tms_i);
|
|
|
uart0_txd_o <= std_logic(uart0_txd_o_int);
|
uart0_txd_o <= std_logic(uart0_txd_o_int);
|
uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
|
uart0_rxd_i_int <= std_ulogic(uart0_rxd_i);
|
uart1_txd_o <= std_logic(uart0_txd_o_int);
|
uart0_rts_o <= std_logic(uart0_rts_o_int);
|
uart1_rxd_i_int <= std_ulogic(uart0_rxd_i);
|
uart0_cts_i_int <= std_ulogic(uart0_cts_i);
|
|
uart1_txd_o <= std_logic(uart1_txd_o_int);
|
|
uart1_rxd_i_int <= std_ulogic(uart1_rxd_i);
|
|
uart1_rts_o <= std_logic(uart1_rts_o_int);
|
|
uart1_cts_i_int <= std_ulogic(uart1_cts_i);
|
|
|
spi_sck_o <= std_logic(spi_sck_o_int);
|
spi_sck_o <= std_logic(spi_sck_o_int);
|
spi_sdo_o <= std_logic(spi_sdo_o_int);
|
spi_sdo_o <= std_logic(spi_sdo_o_int);
|
spi_sdi_i_int <= std_ulogic(spi_sdi_i);
|
spi_sdi_i_int <= std_ulogic(spi_sdi_i);
|
spi_csn_o <= std_logic_vector(spi_csn_o_int);
|
spi_csn_o <= std_logic_vector(spi_csn_o_int);
|
