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[/ ] [neorv32/ ] [trunk/ ] [sim/ ] [README.md ] - Diff between revs 42 and 61
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### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)### [`rtl_modules`](https://github.com/stnolting/neorv32/tree/master/sim/rtl_modules)
This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.This folder provides additional/alternative simulation components (mainly optimized memory components yet). See the comments in the according files for more information.
### [`vivado`](https://github.com/stnolting/neorv32/tree/master/sim/vivado)### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)
This folder provides an example waveform configuration (for Xilinx ISIM simulator) for the default testbench.VUnit testbench for the NEORV32 Processor.
### [`neorv32_tb.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.vhd)### [`neorv32_tb.simple.vhd`](https://github.com/stnolting/neorv32/tree/master/sim/neorv32_tb.simple.vhd)
Default testbench for the NEORV32 Processor.Simple testbench for the NEORV32 Processor.
Simple testbench for the NEORV32 Processor.Simple testbench for the NEORV32 Processor.
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