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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use ieee.math_real.all;
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library neorv32;
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library neorv32;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_package.all;
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use neorv32.neorv32_application_image.all; -- this file is generated by the image generator
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use std.textio.all;
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use std.textio.all;
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entity neorv32_tb is
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entity neorv32_tb is
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end neorv32_tb;
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end neorv32_tb;
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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constant t_clock_c : time := 10 ns; -- main clock period
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constant t_clock_c : time := 10 ns; -- main clock period
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constant f_clock_c : real := 100000000.0; -- main clock in Hz
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constant f_clock_c : real := 100000000.0; -- main clock in Hz
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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constant f_clock_nat_c : natural := 100000000; -- main clock in Hz
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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constant baud_rate_c : real := 19200.0; -- standard UART baudrate
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--
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constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address
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constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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constant wb_mem_size_c : natural := 256; -- wishbone memory size in bytes
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constant wb_mem_latency_c : natural := 8; -- latency in clock cycles (min 1)
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constant wb_mem_latency_c : natural := 8; -- latency in clock cycles (min 1)
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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signal wb_cpu : wishbone_t;
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signal wb_cpu : wishbone_t;
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-- Wishbone memory --
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-- Wishbone memory --
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type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_read_latency_t is array (0 to wb_mem_latency_c-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_read_latency_t is array (0 to wb_mem_latency_c-1) of std_ulogic_vector(31 downto 0);
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-- init function --
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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impure function init_wbmem(init : application_init_image_t) return wb_mem_ram_t is
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variable mem_v : wb_mem_ram_t;
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begin
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mem_v := (others => (others => '0'));
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for i in 0 to init'length-1 loop -- init only in range of source data array
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mem_v(i) := init(i);
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end loop; -- i
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return mem_v;
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end function init_wbmem;
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-- ---------------------------------------------- --
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-- How to simulate a boot from an external memory --
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-- ---------------------------------------------- --
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-- The simulated Wishbone memory can be initialized with the compiled application init.
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-- 1. Uncomment the init_wbmen function below
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-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB)
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-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false)
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-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";)
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-- 5. Simulate!
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signal wb_ram : wb_mem_ram_t;-- := init_wbmem(application_init_image); -- uncomment if you want to init the WB ram with app image
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type wb_mem_t is record
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type wb_mem_t is record
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ram : wb_mem_ram_t;
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rdata : wb_mem_read_latency_t;
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rdata : wb_mem_read_latency_t;
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acc_en : std_ulogic;
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acc_en : std_ulogic;
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ack : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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ack : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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rb_en : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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rb_en : std_ulogic_vector(wb_mem_latency_c-1 downto 0);
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end record;
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end record;
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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MEM_INT_DMEM_USE => true, -- implement processor-internal data memory
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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MEM_INT_DMEM_SIZE => 8*1024, -- size of processor-internal data memory in bytes
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-- External memory interface --
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-- External memory interface --
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MEM_EXT_USE => true, -- implement external memory bus interface?
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MEM_EXT_USE => true, -- implement external memory bus interface?
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MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
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MEM_EXT_REG_STAGES => 2, -- number of interface register stages (0,1,2)
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MEM_EXT_TIMEOUT => 15, -- cycles after which a valid bus access will timeout
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_USE => true, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
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IO_MTIME_USE => true, -- implement machine system timer (MTIME)?
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IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
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IO_UART_USE => true, -- implement universal asynchronous receiver/transmitter (UART)?
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IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
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IO_SPI_USE => true, -- implement serial peripheral interface (SPI)?
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IO_TWI_USE => true, -- implement two-wire interface (TWI)?
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IO_TWI_USE => true, -- implement two-wire interface (TWI)?
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IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
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IO_PWM_USE => true, -- implement pulse-width modulation unit (PWM)?
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IO_WDT_USE => true, -- implement watch dog timer (WDT)?
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IO_WDT_USE => true, -- implement watch dog timer (WDT)?
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IO_TRNG_USE => false, -- DEFAULT TRNG CONFIG CANNOT BE SIMULATED!
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IO_TRNG_USE => false, -- DEFAULT TRNG CONFIG CANNOT BE SIMULATED!
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IO_DEVNULL_USE => true, -- implement dummy device (DEVNULL)?
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IO_CFU_USE => true -- implement custom functions unit (CFU)?
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IO_CFU_USE => true -- implement custom functions unit (CFU)?
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)
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)
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port map (
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port map (
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-- Global control --
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-- Global control --
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clk_i => clk_gen, -- global clock, rising edge
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clk_i => clk_gen, -- global clock, rising edge
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end if;
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end if;
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end if;
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end if;
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end process uart_rx_console;
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end process uart_rx_console;
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-- Wishbone Memory ------------------------------------------------------------------------
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-- Wishbone Memory (simulated external memory) --------------------------------------------
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-- -------------------------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wb_mem_ram_access: process(clk_gen)
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wb_mem_ram_access: process(clk_gen)
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begin
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begin
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if rising_edge(clk_gen) then
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if rising_edge(clk_gen) then
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-- control --
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-- control --
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wb_mem.ack(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en; -- wishbone acknowledge
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wb_mem.ack(0) <= wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en; -- wishbone acknowledge
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-- write access --
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-- write access --
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if ((wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and wb_cpu.we) = '1') then -- valid write access
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if ((wb_cpu.cyc and wb_cpu.stb and wb_mem.acc_en and wb_cpu.we) = '1') then -- valid write access
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for i in 0 to 3 loop
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for i in 0 to 3 loop
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if (wb_cpu.sel(i) = '1') then
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if (wb_cpu.sel(i) = '1') then
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wb_mem.ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
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wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2))))(7+i*8 downto 0+i*8) <= wb_cpu.wdata(7+i*8 downto 0+i*8);
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end if;
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end if;
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end loop; -- i
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end loop; -- i
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end if;
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end if;
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-- read access --
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-- read access --
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wb_mem.rdata(0) <= wb_mem.ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
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wb_mem.rdata(0) <= wb_ram(to_integer(unsigned(wb_cpu.addr(index_size_f(wb_mem_size_c/4)+1 downto 2)))); -- word aligned
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-- virtual read and ack latency --
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-- virtual read and ack latency --
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if (wb_mem_latency_c > 1) then
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if (wb_mem_latency_c > 1) then
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for i in 1 to wb_mem_latency_c-1 loop
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for i in 1 to wb_mem_latency_c-1 loop
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wb_mem.rdata(i) <= wb_mem.rdata(i-1);
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wb_mem.rdata(i) <= wb_mem.rdata(i-1);
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wb_mem.rb_en(i) <= wb_mem.rb_en(i-1);
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wb_mem.rb_en(i) <= wb_mem.rb_en(i-1);
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