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Line 124... |
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-- ---------------------------------------------- --
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-- ---------------------------------------------- --
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-- How to simulate a boot from an external memory --
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-- How to simulate a boot from an external memory --
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-- ---------------------------------------------- --
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-- ---------------------------------------------- --
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-- The simulated Wishbone memory can be initialized with the compiled application init.
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-- The simulated Wishbone memory can be initialized with the compiled application init.
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-- 1. Uncomment the init_wbmen function below
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-- 1. Uncomment the init_wbmen function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image
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-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB)
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-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB)
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-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false)
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-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false)
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-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";)
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-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";)
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-- 5. Simulate!
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-- 5. Simulate!
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-- wishbone memory access? --
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-- wishbone memory access? --
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wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
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wb_mem.acc_en <= '1' when (wb_cpu.addr >= wb_mem_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(wb_mem_base_addr_c) + wb_mem_size_c)) else '0';
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-- output to cpu --
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-- output to cpu --
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wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate
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wb_cpu.rdata <= wb_mem.rdata(wb_mem_latency_c-1) when (wb_mem.rb_en(wb_mem_latency_c-1) = '1') else (others=> '0'); -- data output gate
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wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1);
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wb_cpu.ack <= wb_mem.ack(wb_mem_latency_c-1) and wb_cpu.cyc; -- another AND for classic/standard wishbone transactions
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wb_cpu.err <= '0';
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wb_cpu.err <= '0';
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end neorv32_tb_rtl;
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end neorv32_tb_rtl;
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