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-- #################################################################################################
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-- #################################################################################################
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-- # << NEORV32 - Simple Testbench >> #
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-- # << NEORV32 - Default Testbench >> #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o #
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-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o #
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-- # signals. The received chars are shown in the simulator console and also written to a file #
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-- # signal. The received chars are shown in the simulator console and also written to a file #
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-- # ("neorv32.testbench_uart.out"). #
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-- # ("neorv32.testbench_uart.out"). Futhermore, this testbench provides a simple RAM connected #
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-- # Futhermore, this testbench provides a simple RAM connected to the external Wishbone bus. #
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-- # to the external Wishbone bus. The testbench configures the processor with all optional #
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-- # The testbench configures the processor with all optional element enabled by default. #
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-- # elements enabled by default. #
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-- # ********************************************************************************************* #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # BSD 3-Clause License #
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-- # #
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-- # #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
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-- # #
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-- # #
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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stb : std_ulogic; -- strobe
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stb : std_ulogic; -- strobe
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cyc : std_ulogic; -- valid cycle
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cyc : std_ulogic; -- valid cycle
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ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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tag : std_ulogic_vector(2 downto 0); -- tag
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end record;
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end record;
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signal wb_cpu : wishbone_t;
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signal wb_cpu : wishbone_t;
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-- Wishbone memory --
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-- Wishbone memory --
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type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type wb_mem_ram_t is array (0 to wb_mem_size_c/4-1) of std_ulogic_vector(31 downto 0);
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-- ---------------------------------------------- --
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-- ---------------------------------------------- --
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-- How to simulate a boot from an external memory --
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-- How to simulate a boot from an external memory --
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-- ---------------------------------------------- --
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-- ---------------------------------------------- --
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-- The simulated Wishbone memory can be initialized with the compiled application init.
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-- The simulated Wishbone memory can be initialized with the compiled application init.
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-- 1. Uncomment the init_wbmen function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image
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-- 1. Uncomment the init_wbmem function below; this will initialize the simulated wishbone memory with the neorv32_application_image.vhd image
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-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB)
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-- 2. Increase the wb_mem_size_c constant above to (at least) the size of the application image (like 16kB -> 16*1024)
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-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false)
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-- 3. Disable the processor-internal IMEM in the processor instantiation below (MEM_INT_IMEM_USE => false)
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-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";)
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-- 4. Set the Wishbone memory base address wb_mem_base_addr_c (above) to zero (constant wb_mem_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000";)
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-- 5. Simulate!
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-- 5. Simulate!
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signal wb_ram : wb_mem_ram_t;-- := init_wbmem(application_init_image); -- uncomment if you want to init the WB ram with app image
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signal wb_ram : wb_mem_ram_t;-- := init_wbmem(application_init_image); -- uncomment if you want to init the WB ram with app image
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neorv32_top_inst: neorv32_top
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neorv32_top_inst: neorv32_top
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generic map (
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generic map (
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-- General --
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-- General --
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CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => f_clock_nat_c, -- clock frequency of clk_i in Hz
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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BOOTLOADER_USE => false, -- implement processor-internal bootloader?
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USER_CODE => x"19880704", -- custom user code
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USER_CODE => x"12345678", -- custom user code
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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port map (
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port map (
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-- Global control --
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-- Global control --
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clk_i => clk_gen, -- global clock, rising edge
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clk_i => clk_gen, -- global clock, rising edge
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rstn_i => rst_gen, -- global reset, low-active, async
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rstn_i => rst_gen, -- global reset, low-active, async
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-- Wishbone bus interface --
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-- Wishbone bus interface --
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wb_tag_o => wb_cpu.tag, -- tag
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wb_adr_o => wb_cpu.addr, -- address
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wb_adr_o => wb_cpu.addr, -- address
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wb_dat_i => wb_cpu.rdata, -- read data
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wb_dat_i => wb_cpu.rdata, -- read data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_we_o => wb_cpu.we, -- read/write
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wb_we_o => wb_cpu.we, -- read/write
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wb_sel_o => wb_cpu.sel, -- byte enable
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wb_sel_o => wb_cpu.sel, -- byte enable
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mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_USE = false
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mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_USE = false
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msw_irq_i => '0', -- machine software interrupt
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msw_irq_i => '0', -- machine software interrupt
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mext_irq_i => '0' -- machine external interrupt
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mext_irq_i => '0' -- machine external interrupt
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);
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);
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-- TWI termination --
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-- TWI termination (pull-ups) --
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twi_scl <= 'H';
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twi_scl <= 'H';
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twi_sda <= 'H';
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twi_sda <= 'H';
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-- Console UART Receiver ------------------------------------------------------------------
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-- Console UART Receiver ------------------------------------------------------------------
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