| Line 1... |
Line 1... |
-- #################################################################################################
|
-- #################################################################################################
|
-- # << NEORV32 - Default Testbench >> #
|
-- # << NEORV32 - Default Testbench >> #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # This testbench provides a virtual UART receiver connected to the processor's uart_txd_o #
|
|
-- # signal. The received chars are shown in the simulator console and also written to a file #
|
|
-- # ("neorv32.testbench_uart.out"). #
|
|
-- # #
|
|
-- # Furthermore, this testbench provides two external memories (ext_mem_a and ext_mem_b) coupled #
|
|
-- # via Wishbone. ext_mem_a is initialized with the application_init_image and can be used as #
|
|
-- # external boot memory (external IMEM). #
|
|
-- # ext_mem_b is a small uninitialized memory that can be uased as external memory-mapped IO. #
|
|
-- # #
|
|
-- # Use the "User Configuration" section to configure the testbench according to your need. #
|
-- # Use the "User Configuration" section to configure the testbench according to your need. #
|
|
-- # See NEORV32 data sheet (docs/NEORV32.pdf) for more information. #
|
-- # ********************************************************************************************* #
|
-- # ********************************************************************************************* #
|
-- # BSD 3-Clause License #
|
-- # BSD 3-Clause License #
|
-- # #
|
-- # #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
|
-- # #
|
-- # #
|
| Line 68... |
Line 60... |
constant f_clock_c : natural := 100000000; -- main clock in Hz
|
constant f_clock_c : natural := 100000000; -- main clock in Hz
|
constant baud_rate_c : natural := 19200; -- simulation UART output baudrate
|
constant baud_rate_c : natural := 19200; -- simulation UART output baudrate
|
-- simulated external Wishbone memory A (can be used as external IMEM) --
|
-- simulated external Wishbone memory A (can be used as external IMEM) --
|
constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
|
constant ext_mem_a_base_addr_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- wishbone memory base address (external IMEM base)
|
constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
|
constant ext_mem_a_size_c : natural := imem_size_c; -- wishbone memory size in bytes
|
constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
|
constant ext_mem_a_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
|
-- simulated external Wishbone memory B (can be used as external DMEM) --
|
-- simulated external Wishbone memory B (can be used as external DMEM) --
|
constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
|
constant ext_mem_b_base_addr_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- wishbone memory base address (external DMEM base)
|
constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes
|
constant ext_mem_b_size_c : natural := dmem_size_c; -- wishbone memory size in bytes
|
constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
|
constant ext_mem_b_latency_c : natural := 8; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
|
-- simulated external Wishbone memory C (can be used as external IO) --
|
-- simulated external Wishbone memory C (can be used as external IO) --
|
constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
|
constant ext_mem_c_base_addr_c : std_ulogic_vector(31 downto 0) := x"F0000000"; -- wishbone memory base address (default begin of EXTERNAL IO area)
|
constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes
|
constant ext_mem_c_size_c : natural := 64; -- wishbone memory size in bytes
|
constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initiali delay
|
constant ext_mem_c_latency_c : natural := 3; -- latency in clock cycles (min 1, max 255), plus 1 cycle initial delay
|
|
-- machine interrupt triggers --
|
|
constant msi_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000000"; -- machine software interrupt
|
|
constant mei_trigger_c : std_ulogic_vector(31 downto 0) := x"FF000004"; -- machine external interrupt
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
|
|
-- internals - hands off! --
|
-- internals - hands off! --
|
constant int_imem_c : boolean := not ext_imem_c;
|
constant int_imem_c : boolean := not ext_imem_c;
|
constant int_dmem_c : boolean := not ext_dmem_c;
|
constant int_dmem_c : boolean := not ext_dmem_c;
|
| Line 106... |
Line 101... |
|
|
-- twi --
|
-- twi --
|
signal twi_scl, twi_sda : std_logic;
|
signal twi_scl, twi_sda : std_logic;
|
|
|
-- spi --
|
-- spi --
|
signal spi_data : std_logic;
|
signal spi_data : std_ulogic;
|
|
|
|
-- irq --
|
|
signal msi_ring, mei_ring : std_ulogic;
|
|
|
-- Wishbone bus --
|
-- Wishbone bus --
|
type wishbone_t is record
|
type wishbone_t is record
|
addr : std_ulogic_vector(31 downto 0); -- address
|
addr : std_ulogic_vector(31 downto 0); -- address
|
wdata : std_ulogic_vector(31 downto 0); -- master write data
|
wdata : std_ulogic_vector(31 downto 0); -- master write data
|
| Line 122... |
Line 120... |
ack : std_ulogic; -- transfer acknowledge
|
ack : std_ulogic; -- transfer acknowledge
|
err : std_ulogic; -- transfer error
|
err : std_ulogic; -- transfer error
|
tag : std_ulogic_vector(2 downto 0); -- tag
|
tag : std_ulogic_vector(2 downto 0); -- tag
|
lock : std_ulogic; -- locked/exclusive bus access
|
lock : std_ulogic; -- locked/exclusive bus access
|
end record;
|
end record;
|
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c : wishbone_t;
|
signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_msi, wb_mei : wishbone_t;
|
|
|
-- Wishbone memories --
|
-- Wishbone memories --
|
type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
|
type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
|
type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
|
type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
|
type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
|
type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
|
| Line 137... |
Line 135... |
impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
|
impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
|
variable mem_v : ext_mem_a_ram_t;
|
variable mem_v : ext_mem_a_ram_t;
|
begin
|
begin
|
mem_v := (others => (others => '0'));
|
mem_v := (others => (others => '0'));
|
for i in 0 to init'length-1 loop -- init only in range of source data array
|
for i in 0 to init'length-1 loop -- init only in range of source data array
|
|
if (xbus_big_endian_c = true) then
|
mem_v(i) := init(i);
|
mem_v(i) := init(i);
|
|
else
|
|
mem_v(i) := bswap32_f(init(i));
|
|
end if;
|
end loop; -- i
|
end loop; -- i
|
return mem_v;
|
return mem_v;
|
end function init_wbmem;
|
end function init_wbmem;
|
|
|
-- external memory components --
|
-- external memory components --
|
| Line 184... |
Line 186... |
-- Extension Options --
|
-- Extension Options --
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
FAST_MUL_EN => false, -- use DSPs for M extension's multiplier
|
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
|
FAST_SHIFT_EN => false, -- use barrel shifter for shift operations
|
-- Physical Memory Protection (PMP) --
|
-- Physical Memory Protection (PMP) --
|
PMP_USE => true, -- implement PMP?
|
PMP_USE => true, -- implement PMP?
|
PMP_NUM_REGIONS => 4, -- number of regions (max 16)
|
|
PMP_GRANULARITY => 14, -- minimal region granularity (1=8B, 2=16B, 3=32B, ...) default is 64k
|
|
-- Internal Instruction memory --
|
-- Internal Instruction memory --
|
MEM_INT_IMEM_USE => int_imem_c , -- implement processor-internal instruction memory
|
MEM_INT_IMEM_USE => int_imem_c , -- implement processor-internal instruction memory
|
MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
|
-- Internal Data memory --
|
-- Internal Data memory --
|
| Line 242... |
Line 242... |
-- TWI --
|
-- TWI --
|
twi_sda_io => twi_sda, -- twi serial data line
|
twi_sda_io => twi_sda, -- twi serial data line
|
twi_scl_io => twi_scl, -- twi serial clock line
|
twi_scl_io => twi_scl, -- twi serial clock line
|
-- PWM --
|
-- PWM --
|
pwm_o => open, -- pwm channels
|
pwm_o => open, -- pwm channels
|
|
-- system time input from external MTIME (available if IO_MTIME_USE = false) --
|
|
mtime_i => (others => '0'), -- current system time
|
-- Interrupts --
|
-- Interrupts --
|
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_USE = false
|
mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_USE = false
|
msw_irq_i => '0', -- machine software interrupt
|
msw_irq_i => msi_ring, -- machine software interrupt
|
mext_irq_i => '0' -- machine external interrupt
|
mext_irq_i => mei_ring -- machine external interrupt
|
);
|
);
|
|
|
-- TWI termination (pull-ups) --
|
-- TWI termination (pull-ups) --
|
twi_scl <= 'H';
|
twi_scl <= 'H';
|
twi_sda <= 'H';
|
twi_sda <= 'H';
|
| Line 332... |
Line 334... |
wb_mem_c.sel <= wb_cpu.sel;
|
wb_mem_c.sel <= wb_cpu.sel;
|
wb_mem_c.tag <= wb_cpu.tag;
|
wb_mem_c.tag <= wb_cpu.tag;
|
wb_mem_c.cyc <= wb_cpu.cyc;
|
wb_mem_c.cyc <= wb_cpu.cyc;
|
wb_mem_c.lock <= wb_cpu.lock;
|
wb_mem_c.lock <= wb_cpu.lock;
|
|
|
|
wb_msi.addr <= wb_cpu.addr;
|
|
wb_msi.wdata <= wb_cpu.wdata;
|
|
wb_msi.we <= wb_cpu.we;
|
|
wb_msi.sel <= wb_cpu.sel;
|
|
wb_msi.tag <= wb_cpu.tag;
|
|
wb_msi.cyc <= wb_cpu.cyc;
|
|
wb_msi.lock <= wb_cpu.lock;
|
|
|
|
wb_mei.addr <= wb_cpu.addr;
|
|
wb_mei.wdata <= wb_cpu.wdata;
|
|
wb_mei.we <= wb_cpu.we;
|
|
wb_mei.sel <= wb_cpu.sel;
|
|
wb_mei.tag <= wb_cpu.tag;
|
|
wb_mei.cyc <= wb_cpu.cyc;
|
|
wb_mei.lock <= wb_cpu.lock;
|
|
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata;
|
wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_mei.rdata or wb_msi.rdata;
|
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack;
|
wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_mei.ack or wb_msi.ack;
|
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err;
|
wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_mei.err or wb_msi.err;
|
|
|
-- peripheral select via STROBE signal --
|
-- peripheral select via STROBE signal --
|
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
|
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
|
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
|
wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
|
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
|
wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
|
|
wb_msi.stb <= wb_cpu.stb when (wb_cpu.addr = msi_trigger_c) else '0';
|
|
wb_mei.stb <= wb_cpu.stb when (wb_cpu.addr = mei_trigger_c) else '0';
|
|
|
|
|
-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
|
-- Wishbone Memory A (simulated external IMEM) --------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
-- -------------------------------------------------------------------------------------------
|
ext_mem_a_access: process(clk_gen)
|
ext_mem_a_access: process(clk_gen)
|
| Line 465... |
Line 485... |
end if;
|
end if;
|
end if;
|
end if;
|
end process ext_mem_c_access;
|
end process ext_mem_c_access;
|
|
|
|
|
|
-- Wishbone IRQ Triggers ------------------------------------------------------------------
|
|
-- -------------------------------------------------------------------------------------------
|
|
ext_irq_trigger: process(clk_gen)
|
|
begin
|
|
if rising_edge(clk_gen) then
|
|
-- default --
|
|
msi_ring <= '0';
|
|
wb_msi.rdata <= (others => '0');
|
|
wb_msi.ack <= '0';
|
|
wb_msi.err <= '0';
|
|
mei_ring <= '0';
|
|
wb_mei.rdata <= (others => '0');
|
|
wb_mei.ack <= '0';
|
|
wb_mei.err <= '0';
|
|
|
|
-- machine software interrupt --
|
|
if ((wb_msi.cyc and wb_msi.stb and wb_msi.we) = '1') then
|
|
msi_ring <= '1';
|
|
wb_msi.ack <= '1';
|
|
end if;
|
|
|
|
-- machine external interrupt --
|
|
if ((wb_mei.cyc and wb_mei.stb and wb_mei.we) = '1') then
|
|
mei_ring <= '1';
|
|
wb_mei.ack <= '1';
|
|
end if;
|
|
end if;
|
|
end process ext_irq_trigger;
|
|
|
|
|
end neorv32_tb_rtl;
|
end neorv32_tb_rtl;
|
|
|
No newline at end of file
|
No newline at end of file
|
