| Line 174... |
Line 174... |
generic map (
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generic map (
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-- General --
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-- General --
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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CLOCK_FREQUENCY => f_clock_c, -- clock frequency of clk_i in Hz
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BOOTLOADER_EN => false, -- implement processor-internal bootloader?
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BOOTLOADER_EN => false, -- implement processor-internal bootloader?
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USER_CODE => x"12345678", -- custom user code
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USER_CODE => x"12345678", -- custom user code
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HW_THREAD_ID => x"00000000", -- hardware thread id (hartid)
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HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit)
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
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CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
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CPU_EXTENSION_RISCV_B => true, -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_B => true, -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)?
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IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)?
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_CFS_EN => true, -- implement custom functions subsystem (CFS)?
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IO_CFS_EN => true, -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG => (others => '0') -- custom CFS configuration generic
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IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic
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IO_NCO_EN => true -- implement numerically-controlled oscillator (NCO)?
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)
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)
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port map (
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port map (
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-- Global control --
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-- Global control --
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clk_i => clk_gen, -- global clock, rising edge
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clk_i => clk_gen, -- global clock, rising edge
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rstn_i => rst_gen, -- global reset, low-active, async
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rstn_i => rst_gen, -- global reset, low-active, async
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-- Wishbone bus interface --
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-- Wishbone bus interface (available if MEM_EXT_EN = true) --
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wb_tag_o => wb_cpu.tag, -- tag
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wb_tag_o => wb_cpu.tag, -- tag
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wb_adr_o => wb_cpu.addr, -- address
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wb_adr_o => wb_cpu.addr, -- address
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wb_dat_i => wb_cpu.rdata, -- read data
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wb_dat_i => wb_cpu.rdata, -- read data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_we_o => wb_cpu.we, -- read/write
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wb_we_o => wb_cpu.we, -- read/write
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access
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wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_err_i => wb_cpu.err, -- transfer error
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wb_err_i => wb_cpu.err, -- transfer error
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-- Advanced memory control signals --
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o => open, -- indicates an executed FENCE operation
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fence_o => open, -- indicates an executed FENCE operation
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fencei_o => open, -- indicates an executed FENCEI operation
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fencei_o => open, -- indicates an executed FENCEI operation
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-- GPIO --
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-- GPIO (available if IO_GPIO_EN = true) --
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gpio_o => gpio, -- parallel output
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gpio_o => gpio, -- parallel output
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gpio_i => gpio, -- parallel input
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gpio_i => gpio, -- parallel input
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-- UART --
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-- UART (available if IO_UART_EN = true) --
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uart_txd_o => uart_txd, -- UART send data
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uart_txd_o => uart_txd, -- UART send data
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uart_rxd_i => uart_txd, -- UART receive data
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uart_rxd_i => uart_txd, -- UART receive data
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-- SPI --
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-- SPI (available if IO_SPI_EN = true) --
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spi_sck_o => open, -- SPI serial clock
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spi_sck_o => open, -- SPI serial clock
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spi_sdo_o => spi_data, -- controller data out, peripheral data in
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spi_sdo_o => spi_data, -- controller data out, peripheral data in
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spi_sdi_i => spi_data, -- controller data in, peripheral data out
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spi_sdi_i => spi_data, -- controller data in, peripheral data out
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spi_csn_o => open, -- SPI CS
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spi_csn_o => open, -- SPI CS
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-- TWI --
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-- TWI (available if IO_TWI_EN = true) --
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twi_sda_io => twi_sda, -- twi serial data line
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twi_sda_io => twi_sda, -- twi serial data line
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twi_scl_io => twi_scl, -- twi serial clock line
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twi_scl_io => twi_scl, -- twi serial clock line
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-- PWM --
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-- PWM (available if IO_PWM_EN = true) --
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pwm_o => open, -- pwm channels
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pwm_o => open, -- pwm channels
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-- Custom Functions Subsystem IO --
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-- Custom Functions Subsystem IO --
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cfs_in_i => (others => '0'), -- custom CFS inputs
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cfs_in_i => (others => '0'), -- custom CFS inputs
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cfs_out_o => open, -- custom CFS outputs
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cfs_out_o => open, -- custom CFS outputs
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-- NCO output (available if IO_NCO_EN = true) --
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nco_o => open, -- numerically-controlled oscillator channels
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-- system time input from external MTIME (available if IO_MTIME_EN = false) --
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-- system time input from external MTIME (available if IO_MTIME_EN = false) --
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mtime_i => (others => '0'), -- current system time
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mtime_i => (others => '0'), -- current system time
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-- Interrupts --
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-- Interrupts --
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soc_firq_i => soc_firq_ring, -- fast interrupt channels
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soc_firq_i => soc_firq_ring, -- fast interrupt channels
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mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false
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mtime_irq_i => '0', -- machine software interrupt, available if IO_MTIME_EN = false
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