| Line 132... |
Line 132... |
sel : std_ulogic_vector(03 downto 0); -- byte enable
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sel : std_ulogic_vector(03 downto 0); -- byte enable
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stb : std_ulogic; -- strobe
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stb : std_ulogic; -- strobe
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cyc : std_ulogic; -- valid cycle
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cyc : std_ulogic; -- valid cycle
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ack : std_ulogic; -- transfer acknowledge
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ack : std_ulogic; -- transfer acknowledge
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err : std_ulogic; -- transfer error
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err : std_ulogic; -- transfer error
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tag : std_ulogic_vector(2 downto 0); -- tag
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tag : std_ulogic_vector(03 downto 0); -- request tag
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lock : std_ulogic; -- locked/exclusive bus access
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tag_r : std_ulogic; -- response tag
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end record;
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end record;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
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signal wb_cpu, wb_mem_a, wb_mem_b, wb_mem_c, wb_irq : wishbone_t;
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|
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-- Wishbone memories --
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-- Wishbone memories --
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_a_ram_t is array (0 to ext_mem_a_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_b_ram_t is array (0 to ext_mem_b_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_c_ram_t is array (0 to ext_mem_c_size_c/4-1) of std_ulogic_vector(31 downto 0);
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type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
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type ext_mem_read_latency_t is array (0 to 255) of std_ulogic_vector(31 downto 0);
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|
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-- exclusive access / reservation --
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signal ext_mem_c_atomic_reservation : std_ulogic := '0';
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|
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-- init function --
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-- init function --
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-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
|
-- impure function: returns NOT the same result every time it is evaluated with the same arguments since the source file might have changed
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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variable mem_v : ext_mem_a_ram_t;
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variable mem_v : ext_mem_a_ram_t;
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begin
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begin
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| Line 241... |
Line 244... |
port map (
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port map (
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-- Global control --
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-- Global control --
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clk_i => clk_gen, -- global clock, rising edge
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clk_i => clk_gen, -- global clock, rising edge
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rstn_i => rst_gen, -- global reset, low-active, async
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rstn_i => rst_gen, -- global reset, low-active, async
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-- Wishbone bus interface (available if MEM_EXT_EN = true) --
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-- Wishbone bus interface (available if MEM_EXT_EN = true) --
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wb_tag_o => wb_cpu.tag, -- tag
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wb_tag_o => wb_cpu.tag, -- request tag
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wb_adr_o => wb_cpu.addr, -- address
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wb_adr_o => wb_cpu.addr, -- address
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wb_dat_i => wb_cpu.rdata, -- read data
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wb_dat_i => wb_cpu.rdata, -- read data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_dat_o => wb_cpu.wdata, -- write data
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wb_we_o => wb_cpu.we, -- read/write
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wb_we_o => wb_cpu.we, -- read/write
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wb_sel_o => wb_cpu.sel, -- byte enable
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wb_sel_o => wb_cpu.sel, -- byte enable
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_stb_o => wb_cpu.stb, -- strobe
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_cyc_o => wb_cpu.cyc, -- valid cycle
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wb_lock_o => wb_cpu.lock, -- locked/exclusive bus access
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wb_tag_i => wb_cpu.tag_r, -- response tag
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_ack_i => wb_cpu.ack, -- transfer acknowledge
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wb_err_i => wb_cpu.err, -- transfer error
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wb_err_i => wb_cpu.err, -- transfer error
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-- Advanced memory control signals (available if MEM_EXT_EN = true) --
|
-- Advanced memory control signals (available if MEM_EXT_EN = true) --
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fence_o => open, -- indicates an executed FENCE operation
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fence_o => open, -- indicates an executed FENCE operation
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fencei_o => open, -- indicates an executed FENCEI operation
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fencei_o => open, -- indicates an executed FENCEI operation
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| Line 412... |
Line 415... |
wb_mem_a.wdata <= wb_cpu.wdata;
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wb_mem_a.wdata <= wb_cpu.wdata;
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wb_mem_a.we <= wb_cpu.we;
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wb_mem_a.we <= wb_cpu.we;
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wb_mem_a.sel <= wb_cpu.sel;
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wb_mem_a.sel <= wb_cpu.sel;
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wb_mem_a.tag <= wb_cpu.tag;
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wb_mem_a.tag <= wb_cpu.tag;
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wb_mem_a.cyc <= wb_cpu.cyc;
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wb_mem_a.cyc <= wb_cpu.cyc;
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wb_mem_a.lock <= wb_cpu.lock;
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|
|
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wb_mem_b.addr <= wb_cpu.addr;
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wb_mem_b.addr <= wb_cpu.addr;
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wb_mem_b.wdata <= wb_cpu.wdata;
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wb_mem_b.wdata <= wb_cpu.wdata;
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wb_mem_b.we <= wb_cpu.we;
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wb_mem_b.we <= wb_cpu.we;
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wb_mem_b.sel <= wb_cpu.sel;
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wb_mem_b.sel <= wb_cpu.sel;
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wb_mem_b.tag <= wb_cpu.tag;
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wb_mem_b.tag <= wb_cpu.tag;
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wb_mem_b.cyc <= wb_cpu.cyc;
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wb_mem_b.cyc <= wb_cpu.cyc;
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wb_mem_b.lock <= wb_cpu.lock;
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wb_mem_c.addr <= wb_cpu.addr;
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wb_mem_c.addr <= wb_cpu.addr;
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wb_mem_c.wdata <= wb_cpu.wdata;
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wb_mem_c.wdata <= wb_cpu.wdata;
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wb_mem_c.we <= wb_cpu.we;
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wb_mem_c.we <= wb_cpu.we;
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wb_mem_c.sel <= wb_cpu.sel;
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wb_mem_c.sel <= wb_cpu.sel;
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wb_mem_c.tag <= wb_cpu.tag;
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wb_mem_c.tag <= wb_cpu.tag;
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wb_mem_c.cyc <= wb_cpu.cyc;
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wb_mem_c.cyc <= wb_cpu.cyc;
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wb_mem_c.lock <= wb_cpu.lock;
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|
|
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wb_irq.addr <= wb_cpu.addr;
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wb_irq.addr <= wb_cpu.addr;
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wb_irq.wdata <= wb_cpu.wdata;
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wb_irq.wdata <= wb_cpu.wdata;
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wb_irq.we <= wb_cpu.we;
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wb_irq.we <= wb_cpu.we;
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wb_irq.sel <= wb_cpu.sel;
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wb_irq.sel <= wb_cpu.sel;
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wb_irq.tag <= wb_cpu.tag;
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wb_irq.tag <= wb_cpu.tag;
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wb_irq.cyc <= wb_cpu.cyc;
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wb_irq.cyc <= wb_cpu.cyc;
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wb_irq.lock <= wb_cpu.lock;
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|
|
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
|
-- CPU read-back signals (no mux here since peripherals have "output gates") --
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wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
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wb_cpu.rdata <= wb_mem_a.rdata or wb_mem_b.rdata or wb_mem_c.rdata or wb_irq.rdata;
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wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack;
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wb_cpu.ack <= wb_mem_a.ack or wb_mem_b.ack or wb_mem_c.ack or wb_irq.ack;
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wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err;
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wb_cpu.err <= wb_mem_a.err or wb_mem_b.err or wb_mem_c.err or wb_irq.err;
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wb_cpu.tag_r <= wb_mem_a.tag_r or wb_mem_b.tag_r or wb_mem_c.tag_r or wb_irq.tag_r;
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|
|
-- peripheral select via STROBE signal --
|
-- peripheral select via STROBE signal --
|
wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
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wb_mem_a.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_a_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_a_base_addr_c) + ext_mem_a_size_c)) else '0';
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wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
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wb_mem_b.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_b_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_b_base_addr_c) + ext_mem_b_size_c)) else '0';
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wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
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wb_mem_c.stb <= wb_cpu.stb when (wb_cpu.addr >= ext_mem_c_base_addr_c) and (wb_cpu.addr < std_ulogic_vector(unsigned(ext_mem_c_base_addr_c) + ext_mem_c_size_c)) else '0';
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| Line 479... |
Line 479... |
end loop;
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end loop;
|
end if;
|
end if;
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|
|
-- bus output register --
|
-- bus output register --
|
wb_mem_a.err <= '0';
|
wb_mem_a.err <= '0';
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if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
wb_mem_a.tag_r <= '0';
|
|
if (ext_mem_a.ack(ext_mem_a_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_a.ack = '0') then
|
wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
|
wb_mem_a.rdata <= ext_mem_a.rdata(ext_mem_a_latency_c-1);
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wb_mem_a.ack <= '1';
|
wb_mem_a.ack <= '1';
|
else
|
else
|
wb_mem_a.rdata <= (others => '0');
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wb_mem_a.rdata <= (others => '0');
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wb_mem_a.ack <= '0';
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wb_mem_a.ack <= '0';
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| Line 519... |
Line 520... |
end loop;
|
end loop;
|
end if;
|
end if;
|
|
|
-- bus output register --
|
-- bus output register --
|
wb_mem_b.err <= '0';
|
wb_mem_b.err <= '0';
|
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') then
|
wb_mem_b.tag_r <= '0';
|
|
if (ext_mem_b.ack(ext_mem_b_latency_c-1) = '1') and (wb_mem_b.cyc = '1') and (wb_mem_b.ack = '0') then
|
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
|
wb_mem_b.rdata <= ext_mem_b.rdata(ext_mem_b_latency_c-1);
|
wb_mem_b.ack <= '1';
|
wb_mem_b.ack <= '1';
|
else
|
else
|
wb_mem_b.rdata <= (others => '0');
|
wb_mem_b.rdata <= (others => '0');
|
wb_mem_b.ack <= '0';
|
wb_mem_b.ack <= '0';
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| Line 557... |
Line 559... |
ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
|
ext_mem_c.rdata(i) <= ext_mem_c.rdata(i-1);
|
ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
|
ext_mem_c.ack(i) <= ext_mem_c.ack(i-1) and wb_mem_c.cyc;
|
end loop;
|
end loop;
|
end if;
|
end if;
|
|
|
-- error to simulate interrupted LOCKED/EXCLUSIVE bus access --
|
-- EXCLUSIVE bus access -----------------------------------------------------
|
wb_mem_c.err <= wb_mem_c.cyc and wb_mem_c.stb and wb_mem_c.lock and wb_mem_c.addr(2); -- locked access to odd word-addresses will fail
|
-- -----------------------------------------------------------------------------
|
|
-- make a reservation --
|
|
if ((wb_mem_c.cyc and wb_mem_c.stb) = '1') and -- valid access
|
|
(wb_mem_c.tag(3) = '1') and -- make a reservation if there is a request (LR.W instruction)
|
|
(wb_mem_c.addr(2) = '0') then -- only possible for even word-addresses - odd word-addresses will fail
|
|
ext_mem_c_atomic_reservation <= '1';
|
|
-- clear reservation --
|
|
elsif (wb_mem_c.ack = '1') and -- end of access
|
|
(wb_mem_c.tag(3) = '0') then -- end of exclusive access
|
|
ext_mem_c_atomic_reservation <= '0';
|
|
end if;
|
|
-- -----------------------------------------------------------------------------
|
|
|
-- bus output register --
|
-- bus output register --
|
if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') then
|
wb_mem_c.err <= '0';
|
|
if (ext_mem_c.ack(ext_mem_c_latency_c-1) = '1') and (wb_mem_c.cyc = '1') and (wb_mem_c.ack = '0') then
|
wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
|
wb_mem_c.rdata <= ext_mem_c.rdata(ext_mem_c_latency_c-1);
|
wb_mem_c.ack <= '1';
|
wb_mem_c.ack <= '1';
|
|
wb_mem_c.tag_r <= ext_mem_c_atomic_reservation;
|
else
|
else
|
wb_mem_c.rdata <= (others => '0');
|
wb_mem_c.rdata <= (others => '0');
|
wb_mem_c.ack <= '0';
|
wb_mem_c.ack <= '0';
|
|
wb_mem_c.tag_r <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process ext_mem_c_access;
|
end process ext_mem_c_access;
|
|
|
|
|
| Line 581... |
Line 597... |
if rising_edge(clk_gen) then
|
if rising_edge(clk_gen) then
|
-- bus interface --
|
-- bus interface --
|
wb_irq.rdata <= (others => '0');
|
wb_irq.rdata <= (others => '0');
|
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
|
wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
|
wb_irq.err <= '0';
|
wb_irq.err <= '0';
|
|
wb_irq.tag_r <= '0';
|
-- trigger IRQ using CSR.MIE bit layout --
|
-- trigger IRQ using CSR.MIE bit layout --
|
msi_ring <= '0';
|
msi_ring <= '0';
|
mei_ring <= '0';
|
mei_ring <= '0';
|
soc_firq_ring <= (others => '0');
|
soc_firq_ring <= (others => '0');
|
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
|
if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
|
