| Line 153... |
Line 153... |
impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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impure function init_wbmem(init : application_init_image_t) return ext_mem_a_ram_t is
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variable mem_v : ext_mem_a_ram_t;
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variable mem_v : ext_mem_a_ram_t;
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begin
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begin
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mem_v := (others => (others => '0'));
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mem_v := (others => (others => '0'));
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for i in 0 to init'length-1 loop -- init only in range of source data array
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for i in 0 to init'length-1 loop -- init only in range of source data array
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if (xbus_big_endian_c = true) then
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if (xbus_big_endian_c = false) then
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mem_v(i) := init(i);
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mem_v(i) := init(i);
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else
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else
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mem_v(i) := bswap32_f(init(i));
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mem_v(i) := bswap32_f(init(i));
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end if;
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end if;
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end loop; -- i
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end loop; -- i
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| Line 195... |
Line 195... |
HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit)
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HW_THREAD_ID => 0, -- hardware thread id (hartid) (32-bit)
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-- On-Chip Debugger (OCD) --
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-- On-Chip Debugger (OCD) --
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ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger
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ON_CHIP_DEBUGGER_EN => true, -- implement on-chip debugger
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-- RISC-V CPU Extensions --
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-- RISC-V CPU Extensions --
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CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
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CPU_EXTENSION_RISCV_A => true, -- implement atomic extension?
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CPU_EXTENSION_RISCV_B => true, -- implement bit manipulation extensions?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_U => true, -- implement user mode extension?
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CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
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CPU_EXTENSION_RISCV_Zfinx => true, -- implement 32-bit floating-point extension (using INT reg!)
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| Line 213... |
Line 212... |
-- Physical Memory Protection (PMP) --
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-- Physical Memory Protection (PMP) --
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PMP_NUM_REGIONS => 5, -- number of regions (0..64)
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PMP_NUM_REGIONS => 5, -- number of regions (0..64)
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PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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PMP_MIN_GRANULARITY => 64*1024, -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
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-- Hardware Performance Monitors (HPM) --
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-- Hardware Performance Monitors (HPM) --
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HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29)
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HPM_NUM_CNTS => 12, -- number of implemented HPM counters (0..29)
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HPM_CNT_WIDTH => 40, -- total size of HPM counters (1..64)
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HPM_CNT_WIDTH => 40, -- total size of HPM counters (0..64)
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-- Internal Instruction memory --
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-- Internal Instruction memory --
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MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory
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MEM_INT_IMEM_EN => int_imem_c , -- implement processor-internal instruction memory
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MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_SIZE => imem_size_c, -- size of processor-internal instruction memory in bytes
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MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
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MEM_INT_IMEM_ROM => false, -- implement processor-internal instruction memory as ROM
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-- Internal Data memory --
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-- Internal Data memory --
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| Line 236... |
Line 235... |
IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
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IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_PWM_EN => true, -- implement pulse-width modulation unit (PWM)?
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IO_PWM_NUM_CH => 30, -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_CFS_EN => true, -- implement custom functions subsystem (CFS)?
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IO_CFS_EN => true, -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic
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IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic
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IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
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| Line 292... |
Line 291... |
spi_sdi_i => spi_data, -- controller data in, peripheral data out
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spi_sdi_i => spi_data, -- controller data in, peripheral data out
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spi_csn_o => open, -- SPI CS
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spi_csn_o => open, -- SPI CS
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-- TWI (available if IO_TWI_EN = true) --
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-- TWI (available if IO_TWI_EN = true) --
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twi_sda_io => twi_sda, -- twi serial data line
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twi_sda_io => twi_sda, -- twi serial data line
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twi_scl_io => twi_scl, -- twi serial clock line
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twi_scl_io => twi_scl, -- twi serial clock line
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-- PWM (available if IO_PWM_EN = true) --
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-- PWM (available if IO_PWM_NUM_CH > 0) --
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pwm_o => open, -- pwm channels
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pwm_o => open, -- pwm channels
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-- Custom Functions Subsystem IO --
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-- Custom Functions Subsystem IO --
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cfs_in_i => (others => '0'), -- custom CFS inputs
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cfs_in_i => (others => '0'), -- custom CFS inputs
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cfs_out_o => open, -- custom CFS outputs
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cfs_out_o => open, -- custom CFS outputs
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-- NCO output (available if IO_NCO_EN = true) --
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-- NCO output (available if IO_NCO_EN = true) --
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| Line 601... |
Line 600... |
irq_trigger: process(clk_gen)
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irq_trigger: process(clk_gen)
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begin
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begin
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if rising_edge(clk_gen) then
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if rising_edge(clk_gen) then
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-- bus interface --
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-- bus interface --
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wb_irq.rdata <= (others => '0');
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wb_irq.rdata <= (others => '0');
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel);
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wb_irq.ack <= wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel);
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wb_irq.err <= '0';
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wb_irq.err <= '0';
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-- trigger IRQ using CSR.MIE bit layout --
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-- trigger IRQ using CSR.MIE bit layout --
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nmi_ring <= '0';
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nmi_ring <= '0';
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msi_ring <= '0';
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msi_ring <= '0';
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mei_ring <= '0';
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mei_ring <= '0';
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soc_firq_ring <= (others => '0');
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soc_firq_ring <= (others => '0');
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_all_f(wb_irq.sel)) = '1') then
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if ((wb_irq.cyc and wb_irq.stb and wb_irq.we and and_reduce_f(wb_irq.sel)) = '1') then
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nmi_ring <= wb_irq.wdata(00); -- non-maskable interrupt
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nmi_ring <= wb_irq.wdata(00); -- non-maskable interrupt
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msi_ring <= wb_irq.wdata(03); -- machine software interrupt
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msi_ring <= wb_irq.wdata(03); -- machine software interrupt
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mei_ring <= wb_irq.wdata(11); -- machine software interrupt
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mei_ring <= wb_irq.wdata(11); -- machine software interrupt
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--
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--
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soc_firq_ring(0) <= wb_irq.wdata(26); -- fast interrupt SoC channel 0 (-> FIRQ channel 10)
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soc_firq_ring(0) <= wb_irq.wdata(26); -- fast interrupt SoC channel 0 (-> FIRQ channel 10)
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