URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sim/] [neorv32_tb.vhd] - Diff between revs 6 and 8

Rev 6	Rev 8
Line 132...	Line 132...
`-- RISC-V CPU Extensions --`	`-- RISC-V CPU Extensions --`
`CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?`	`CPU_EXTENSION_RISCV_C => true, -- implement compressed extension?`
`CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?`	`CPU_EXTENSION_RISCV_E => false, -- implement embedded RF extension?`
`CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?`	`CPU_EXTENSION_RISCV_M => true, -- implement muld/div extension?`
`CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?`	`CPU_EXTENSION_RISCV_Zicsr => true, -- implement CSR system?`
	`CPU_EXTENSION_RISCV_Zifencei => true, -- implement instruction stream sync.?`
`-- Memory configuration: Instruction memory --`	`-- Memory configuration: Instruction memory --`
`MEM_ISPACE_BASE => x"00000000", -- base address of instruction memory space`	`MEM_ISPACE_BASE => x"00000000", -- base address of instruction memory space`
`MEM_ISPACE_SIZE => 16*1024, -- total size of instruction memory space in byte`	`MEM_ISPACE_SIZE => 16*1024, -- total size of instruction memory space in byte`
`MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory`	`MEM_INT_IMEM_USE => true, -- implement processor-internal instruction memory`
`MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes`	`MEM_INT_IMEM_SIZE => 16*1024, -- size of processor-internal instruction memory in bytes`