| Line 220... |
Line 220... |
XIRQ_TRIGGER_POLARITY => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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XIRQ_TRIGGER_POLARITY => (others => '1'), -- trigger polarity: 0=low-level/falling-edge, 1=high-level/rising-edge
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-- Processor peripherals --
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-- Processor peripherals --
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
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IO_GPIO_EN => true, -- implement general purpose input/output port unit (GPIO)?
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_MTIME_EN => true, -- implement machine system timer (MTIME)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_EN => true, -- implement primary universal asynchronous receiver/transmitter (UART0)?
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IO_UART0_RX_FIFO => 32, -- RX fifo depth, has to be a power of two, min 1
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IO_UART0_TX_FIFO => 32, -- TX fifo depth, has to be a power of two, min 1
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IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_EN => true, -- implement secondary universal asynchronous receiver/transmitter (UART1)?
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IO_UART1_RX_FIFO => 1, -- RX fifo depth, has to be a power of two, min 1
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IO_UART1_TX_FIFO => 1, -- TX fifo depth, has to be a power of two, min 1
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IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
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IO_SPI_EN => true, -- implement serial peripheral interface (SPI)?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_TWI_EN => true, -- implement two-wire interface (TWI)?
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IO_PWM_NUM_CH => 30, -- number of PWM channels to implement (0..60); 0 = disabled
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IO_PWM_NUM_CH => 30, -- number of PWM channels to implement (0..60); 0 = disabled
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_WDT_EN => true, -- implement watch dog timer (WDT)?
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_TRNG_EN => false, -- trng cannot be simulated
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IO_CFS_EN => true, -- implement custom functions subsystem (CFS)?
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IO_CFS_EN => true, -- implement custom functions subsystem (CFS)?
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IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic
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IO_CFS_CONFIG => (others => '0'), -- custom CFS configuration generic
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IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
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IO_CFS_IN_SIZE => 32, -- size of CFS input conduit in bits
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IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits
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IO_CFS_OUT_SIZE => 32, -- size of CFS output conduit in bits
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IO_NEOLED_EN => true -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_EN => true, -- implement NeoPixel-compatible smart LED interface (NEOLED)?
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IO_NEOLED_TX_FIFO => 8 -- NEOLED TX FIFO depth, 1..32k, has to be a power of two
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)
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)
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port map (
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port map (
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-- Global control --
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-- Global control --
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clk_i => clk_gen, -- global clock, rising edge
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clk_i => clk_gen, -- global clock, rising edge
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rstn_i => rst_gen, -- global reset, low-active, async
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rstn_i => rst_gen, -- global reset, low-active, async
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