| Line 41... |
Line 41... |
.balign 4
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.balign 4
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.global _start
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.global _start
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// IO region
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// IO region
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.set IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
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.equ IO_BEGIN, 0xFFFFFF80 // start of processor-internal IO region
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// SYSINFO
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// SYSINFO
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.set SYSINFO_DSPACE_BASE, 0xFFFFFFF4
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.equ SYSINFO_DSPACE_BASE, 0xFFFFFFF4
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.set SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
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.equ SYSINFO_DSPACE_SIZE, 0xFFFFFFFC
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_start:
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_start:
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.cfi_startproc
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.cfi_startproc
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.cfi_undefined ra
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.cfi_undefined ra
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// *********************************************************
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// *********************************************************
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// Clear register file
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// Clear register file
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// *********************************************************
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// *********************************************************
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__crt0_reg_file_clear:
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__crt0_reg_file_clear:
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addi x0, x0, 0 // hardwired to zero
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//addi x0, x0, 0 // hardwired to zero
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addi x1, x0, 0
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addi x1, x0, 0
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__crt0_reg_file_init:
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addi x2, x1, 0
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addi x2, x1, 0
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addi x3, x2, 0
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addi x3, x2, 0
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addi x4, x3, 0
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addi x4, x3, 0
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addi x5, x4, 0
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addi x5, x4, 0
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addi x6, x5, 0
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addi x6, x5, 0
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| Line 76... |
Line 75... |
addi x14, x13, 0
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addi x14, x13, 0
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addi x15, x14, 0
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addi x15, x14, 0
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// the following registers do not exist in rv32e
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// the following registers do not exist in rv32e
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// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when
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// "__RISCV_EMBEDDED_CPU__" is automatically defined by the makefiles when
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// compiling for a rv32e architecture
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// compiling for a rv32e* architecture
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#ifndef __RISCV_EMBEDDED_CPU__
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#ifndef __RISCV_EMBEDDED_CPU__
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addi x16, x15, 0
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addi x16, x15, 0
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addi x17, x16, 0
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addi x17, x16, 0
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addi x18, x17, 0
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addi x18, x17, 0
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addi x19, x18, 0
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addi x19, x18, 0
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| Line 98... |
Line 97... |
addi x31, x30, 0
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addi x31, x30, 0
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#endif
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#endif
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// *********************************************************
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// *********************************************************
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// TEST AREA / DANGER ZONE / IDEA-LAB
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// TEST AREA / DANGER ZONE
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// *********************************************************
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// *********************************************************
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__crt0_tests:
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__crt0_tests:
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nop
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nop
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| Line 126... |
Line 125... |
la gp, __global_pointer$
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la gp, __global_pointer$
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.option pop
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.option pop
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// *********************************************************
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// *********************************************************
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// Init exception vector table (2x16 4-byte entries) with dummy handlers
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// Init trap handler base address
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// *********************************************************
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// *********************************************************
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__crt0_neorv32_rte_init:
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__crt0_neorv32_trap_init:
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la x11, __crt0_neorv32_rte
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la x11, __crt0_dummy_trap_handler
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csrw mtvec, x11 // set address of first-level exception handler
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csrw mtvec, x11 // set address of first-level exception handler
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lw x11, SYSINFO_DSPACE_BASE(zero) // data memory space base address
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la x12, __crt0_neorv32_rte_dummy_hanlder
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li x13, 2*16 // number of entries (16xEXC, 16xIRQ)
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__crt0_neorv32_rte_init_loop:
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sw x12, 0(x11) // set dummy handler
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add x11, x11, 4
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add x13, x13, -1
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bne zero, x13, __crt0_neorv32_rte_init_loop
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// *********************************************************
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// *********************************************************
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// Reset/deactivate IO/peripheral devices
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// Reset/deactivate IO/peripheral devices
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// Devices, that are not implemented, will cause a store access fault
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// Devices, that are not implemented, will cause a store access fault
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// which is captured but actually ignored due to the dummy handler.
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// which is captured but actually ignored due to the dummy handler.
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| Line 214... |
Line 203... |
__crt0_this_is_the_end_end:
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__crt0_this_is_the_end_end:
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j __crt0_this_is_the_end_end // in case Ziscr is not available
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j __crt0_this_is_the_end_end // in case Ziscr is not available
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// *********************************************************
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// *********************************************************
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// NEORV32 runtime environment: First-level exception/interrupt handler
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// dummy trap handler (for exceptions & IRQs)
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// tries to move on to next instruction
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// *********************************************************
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// *********************************************************
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.align 4
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.global __crt0_dummy_trap_handler
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__crt0_neorv32_rte:
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.balign 4
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__crt0_dummy_trap_handler:
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// --------------------------------------------
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addi sp, sp, -8
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// full context save
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sw x8, 0(sp)
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// --------------------------------------------
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sw x9, 4(sp)
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#ifndef __RISCV_EMBEDDED_CPU__
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addi sp, sp, -120
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#else
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addi sp, sp, -56
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#endif
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sw ra,0(sp)
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csrr x8, mcause
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sw gp,4(sp)
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blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt
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sw tp,8(sp)
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sw t0,12(sp)
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sw t1,16(sp)
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sw t2,20(sp)
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sw s0,24(sp)
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sw s1,28(sp)
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sw a0,32(sp)
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sw a1,36(sp)
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sw a2,40(sp)
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sw a3,44(sp)
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sw a4,48(sp)
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sw a5,52(sp)
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#ifndef __RISCV_EMBEDDED_CPU__
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sw a6,56(sp)
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sw a7,60(sp)
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sw s2,64(sp)
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sw s3,68(sp)
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sw s4,72(sp)
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sw s5,76(sp)
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sw s6,80(sp)
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sw s7,84(sp)
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sw s8,88(sp)
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sw s9,92(sp)
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sw s10,96(sp)
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sw s11,100(sp)
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sw t3,104(sp)
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sw t4,108(sp)
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sw t5,112(sp)
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sw t6,116(sp)
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#endif
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__crt0_dummy_trap_handler_compute_return:
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csrr x8, mepc
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// --------------------------------------------
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// is compressed instruction?
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// get cause and prepare jump into vector table
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lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
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// --------------------------------------------
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andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
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csrr t0, mcause // get cause code
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andi t1, t0, 0x0f // isolate cause ID
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slli t1, t1, 2 // make address offset
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lw ra, SYSINFO_DSPACE_BASE(zero) // data memory space base address
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add t1, t1, ra // get vetor table entry address (EXC vectors)
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csrr ra, mepc // get return address
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blt t0, zero, __crt0_neorv32_rte_is_irq // branch if this is an INTERRUPT
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// --------------------------------------------
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// compute return address for EXCEPTIONS only
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// --------------------------------------------
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__crt0_neorv32_rte_is_exc:
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// check if faulting instruction is compressed and adjust return address
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lh t0, 0(ra) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
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addi t2, zero, 3 // mask
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and t0, t0, t2 // isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
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addi ra, ra, +2 // only this for compressed instructions
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bne t0, t2, __crt0_neorv32_rte_execute // jump if compressed instruction
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addi ra, ra, +2 // add another 2 (making +4) for uncompressed instructions
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j __crt0_neorv32_rte_execute
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// --------------------------------------------
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// vector table offset for INTERRUPTS only
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// --------------------------------------------
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__crt0_neorv32_rte_is_irq:
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addi t1, t1, 16*4
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// --------------------------------------------
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// call handler from vector table
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// --------------------------------------------
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__crt0_neorv32_rte_execute:
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lw t0, 0(t1) // get base address of second-level handler
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// push ra
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addi sp, sp, -4
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sw ra, 0(sp)
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jalr ra, t0 // call second-level handler
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// pop ra
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lw ra, 0(sp)
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addi sp, sp, +4
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csrw mepc, ra
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// --------------------------------------------
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// full context restore
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// --------------------------------------------
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lw ra,0(sp)
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lw gp,4(sp)
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lw tp,8(sp)
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lw t0,12(sp)
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lw t1,16(sp)
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lw t2,20(sp)
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lw s0,24(sp)
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lw s1,28(sp)
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lw a0,32(sp)
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lw a1,36(sp)
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lw a2,40(sp)
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lw a3,44(sp)
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lw a4,48(sp)
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lw a5,52(sp)
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#ifndef __RISCV_EMBEDDED_CPU__
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lw a6,56(sp)
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lw a7,60(sp)
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lw s2,64(sp)
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lw s3,68(sp)
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lw s4,72(sp)
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lw s5,76(sp)
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lw s6,80(sp)
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lw s7,84(sp)
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lw s8,88(sp)
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lw s9,92(sp)
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lw s10,96(sp)
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lw s11,100(sp)
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lw t3,104(sp)
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lw t4,108(sp)
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lw t5,112(sp)
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lw t6,116(sp)
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#endif
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#ifndef __RISCV_EMBEDDED_CPU__
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addi x8, x8, +2 // only this for compressed instructions
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addi sp, sp, +120
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csrw mepc, x8 // set return address when compressed instruction
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#else
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addi sp, sp, +56
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#endif
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addi x8, zero, 3
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bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
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// --------------------------------------------
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// is uncompressed instruction
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// this is the ONLY place where MRET should be used!
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csrr x8, mepc
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// --------------------------------------------
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addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions
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mret
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csrw mepc, x8
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__crt0_dummy_trap_handler_irq:
|
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// *********************************************************
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lw x9, 0(sp)
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// Dummy exception handler: just move on to next instruction
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lw x8, 4(sp)
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// *********************************************************
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addi sp, sp, +8
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__crt0_neorv32_rte_dummy_hanlder:
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ret
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mret
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.cfi_endproc
|
.cfi_endproc
|
.end
|
.end
|
