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Line 40... |
.section .text
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.section .text
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.balign 4
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.balign 4
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.global _start
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.global _start
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// standard CSRs
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.set mtinst, 0x34a
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// custom CSRs
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// custom CSRs
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.set CSR_MISPACEBASE, 0xfc4 // CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */
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.set CSR_MISPACEBASE, 0xfc4 // CUSTOM (r/-): Base address of instruction memory space (via MEM_ISPACE_BASE generic) */
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.set CSR_MDSPACEBASE, 0xfc5 // CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */
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.set CSR_MDSPACEBASE, 0xfc5 // CUSTOM (r/-): Base address of data memory space (via MEM_DSPACE_BASE generic) */
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.set CSR_MISPACESIZE, 0xfc6 // CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */
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.set CSR_MISPACESIZE, 0xfc6 // CUSTOM (r/-): Total size of instruction memory space in byte (via MEM_ISPACE_SIZE generic) */
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.set CSR_MDSPACESIZE, 0xfc7 // CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */
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.set CSR_MDSPACESIZE, 0xfc7 // CUSTOM (r/-): Total size of data memory space in byte (via MEM_DSPACE_SIZE generic) */
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// --------------------------------------------
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// --------------------------------------------
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// compute return address for EXCEPTIONS only
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// compute return address for EXCEPTIONS only
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// --------------------------------------------
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// --------------------------------------------
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__crt0_neorv32_rte_is_exc:
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__crt0_neorv32_rte_is_exc:
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// is faulting instruction compressed?
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// check if faulting instruction is compressed and adjust return address
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csrr t0, mtinst
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andi t0, t0, 2 // get compression flag (bit #1): 0=compressed, 1=uncompressed
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lh t0, 0(ra) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
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addi t2, zero, 3 // mask
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and t0, t0, t2 // isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
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addi ra, ra, +2 // only this for compressed instructions
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addi ra, ra, +2 // only this for compressed instructions
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add ra, ra, t0 // add another 2 (making +4) for uncompressed instructions
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bne t0, t2, __crt0_neorv32_rte_execute // jump if compressed instruction
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addi ra, ra, +2 // add another 2 (making +4) for uncompressed instructions
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j __crt0_neorv32_rte_execute
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j __crt0_neorv32_rte_execute
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// --------------------------------------------
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// --------------------------------------------
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// vector table offset for INTERRUPTS only
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// vector table offset for INTERRUPTS only
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