| Line 80... |
Line 80... |
#define RUN_SGNINJ_TESTS (1)
|
#define RUN_SGNINJ_TESTS (1)
|
//** Run classify tests when != 0 */
|
//** Run classify tests when != 0 */
|
#define RUN_CLASSIFY_TESTS (1)
|
#define RUN_CLASSIFY_TESTS (1)
|
//** Run unsupported instructions tests when != 0 */
|
//** Run unsupported instructions tests when != 0 */
|
#define RUN_UNAVAIL_TESTS (1)
|
#define RUN_UNAVAIL_TESTS (1)
|
|
//** Run average instruction execution time test when != 0 */
|
|
#define RUN_TIMING_TESTS (0)
|
/**@}*/
|
/**@}*/
|
|
|
|
|
// Prototypes
|
// Prototypes
|
uint32_t get_test_vector(void);
|
uint32_t get_test_vector(void);
|
| Line 141... |
Line 143... |
// intro
|
// intro
|
neorv32_uart_printf("<<< Zfinx extension test >>>\n");
|
neorv32_uart_printf("<<< Zfinx extension test >>>\n");
|
#if (SILENT_MODE != 0)
|
#if (SILENT_MODE != 0)
|
neorv32_uart_printf("SILENT_MODE enabled (only showing actual errors)\n");
|
neorv32_uart_printf("SILENT_MODE enabled (only showing actual errors)\n");
|
#endif
|
#endif
|
neorv32_uart_printf("Test cases per instruction: %u\n\n", (uint32_t)NUM_TEST_CASES);
|
neorv32_uart_printf("Test cases per instruction: %u\n", (uint32_t)NUM_TEST_CASES);
|
|
neorv32_uart_printf("NOTE: The NEORV32 FPU does not support subnormal numbers yet. Subnormal numbers are flushed to zero.\n\n");
|
|
|
|
|
// clear exception status word
|
// clear exception status word
|
neorv32_cpu_csr_write(CSR_FFLAGS, 0);; // real hardware
|
neorv32_cpu_csr_write(CSR_FFLAGS, 0);; // real hardware
|
feclearexcept(FE_ALL_EXCEPT); // software runtime (GCC floating-point emulation)
|
feclearexcept(FE_ALL_EXCEPT); // software runtime (GCC floating-point emulation)
|
| Line 411... |
Line 414... |
neorv32_uart_printf("\n# unsupported FDIV.S (division) [illegal instruction]...\n");
|
neorv32_uart_printf("\n# unsupported FDIV.S (division) [illegal instruction]...\n");
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
opa.binary_value = get_test_vector();
|
opa.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
riscv_intrinsic_fdivs(opa.float_value, opb.float_value);
|
riscv_intrinsic_fdivs(opa.float_value, opb.float_value);
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_I_ILLEGAL) {
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
err_cnt_total++;
|
err_cnt_total++;
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
| Line 424... |
Line 427... |
neorv32_uart_printf("\n# unsupported FSQRT.S (square root) [illegal instruction]...\n");
|
neorv32_uart_printf("\n# unsupported FSQRT.S (square root) [illegal instruction]...\n");
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
opa.binary_value = get_test_vector();
|
opa.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
riscv_intrinsic_fsqrts(opa.float_value);
|
riscv_intrinsic_fsqrts(opa.float_value);
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_I_ILLEGAL) {
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
err_cnt_total++;
|
err_cnt_total++;
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
| Line 437... |
Line 440... |
neorv32_uart_printf("\n# unsupported FMADD.S (fused multiply-add) [illegal instruction]...\n");
|
neorv32_uart_printf("\n# unsupported FMADD.S (fused multiply-add) [illegal instruction]...\n");
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
opa.binary_value = get_test_vector();
|
opa.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
riscv_intrinsic_fmadds(opa.float_value, opb.float_value, -opa.float_value);
|
riscv_intrinsic_fmadds(opa.float_value, opb.float_value, -opa.float_value);
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_I_ILLEGAL) {
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
err_cnt_total++;
|
err_cnt_total++;
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
| Line 450... |
Line 453... |
neorv32_uart_printf("\n# unsupported FMSUB.S (fused multiply-sub) [illegal instruction]...\n");
|
neorv32_uart_printf("\n# unsupported FMSUB.S (fused multiply-sub) [illegal instruction]...\n");
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
opa.binary_value = get_test_vector();
|
opa.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
riscv_intrinsic_fmsubs(opa.float_value, opb.float_value, -opa.float_value);
|
riscv_intrinsic_fmsubs(opa.float_value, opb.float_value, -opa.float_value);
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_I_ILLEGAL) {
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
err_cnt_total++;
|
err_cnt_total++;
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
| Line 463... |
Line 466... |
neorv32_uart_printf("\n# unsupported FNMSUB.S (fused negated multiply-sub) [illegal instruction]...\n");
|
neorv32_uart_printf("\n# unsupported FNMSUB.S (fused negated multiply-sub) [illegal instruction]...\n");
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
opa.binary_value = get_test_vector();
|
opa.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
riscv_intrinsic_fnmadds(opa.float_value, opb.float_value, -opa.float_value);
|
riscv_intrinsic_fnmadds(opa.float_value, opb.float_value, -opa.float_value);
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_I_ILLEGAL) {
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
err_cnt_total++;
|
err_cnt_total++;
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
| Line 476... |
Line 479... |
neorv32_uart_printf("\n# unsupported FNMADD.S (fused negated multiply-add) [illegal instruction]...\n");
|
neorv32_uart_printf("\n# unsupported FNMADD.S (fused negated multiply-add) [illegal instruction]...\n");
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
neorv32_cpu_csr_write(CSR_MCAUSE, 0);
|
opa.binary_value = get_test_vector();
|
opa.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
opb.binary_value = get_test_vector();
|
riscv_intrinsic_fnmadds(opa.float_value, opb.float_value, -opa.float_value);
|
riscv_intrinsic_fnmadds(opa.float_value, opb.float_value, -opa.float_value);
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
|
if (neorv32_cpu_csr_read(CSR_MCAUSE) != TRAP_CODE_I_ILLEGAL) {
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[FAILED]%c[0m\n", 27, 27);
|
err_cnt_total++;
|
err_cnt_total++;
|
}
|
}
|
else {
|
else {
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%c[1m[ok]%c[0m\n", 27, 27);
|
}
|
}
|
#endif
|
#endif
|
|
|
|
|
// final report
|
// ----------------------------------------------------------------------------
|
|
// Instruction execution timing test
|
|
// ----------------------------------------------------------------------------
|
|
|
|
#if (RUN_TIMING_TESTS != 0)
|
|
|
|
uint32_t time_start, time_sw, time_hw;
|
|
const uint32_t num_runs = 4096;
|
|
|
|
neorv32_uart_printf("\nAverage execution time tests (%u runs)\n", num_runs);
|
|
|
|
|
|
// signed integer to float
|
|
neorv32_uart_printf("FCVT.S.W: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.float_value = riscv_intrinsic_fcvt_sw((int32_t)opa.binary_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.float_value = riscv_emulate_fcvt_sw((int32_t)opa.binary_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
|
|
|
|
// float to signed integer
|
|
neorv32_uart_printf("FCVT.W.S: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.binary_value = (uint32_t)riscv_intrinsic_fcvt_ws(opa.float_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.binary_value = (uint32_t)riscv_emulate_fcvt_ws(opa.float_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
|
|
|
|
// addition
|
|
neorv32_uart_printf("FADD.S: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
opb.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.float_value = riscv_intrinsic_fadds(opa.float_value, opb.float_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.float_value = riscv_emulate_fadds(opa.float_value, opb.float_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
|
|
|
|
// subtraction
|
|
neorv32_uart_printf("FSUB.S: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
opb.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.float_value = riscv_intrinsic_fsubs(opa.float_value, opb.float_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.float_value = riscv_emulate_fsubs(opa.float_value, opb.float_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
|
|
|
|
// multiplication
|
|
neorv32_uart_printf("FMUL.S: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
opb.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.float_value = riscv_intrinsic_fmuls(opa.float_value, opb.float_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.float_value = riscv_emulate_fmuls(opa.float_value, opb.float_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
|
|
|
|
// Max
|
|
neorv32_uart_printf("FMAX.S: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
opb.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.float_value = riscv_intrinsic_fmaxs(opa.float_value, opb.float_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.float_value = riscv_emulate_fmaxs(opa.float_value, opb.float_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
|
|
|
|
// Comparison
|
|
neorv32_uart_printf("FLE.S: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
opb.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.float_value = riscv_intrinsic_fles(opa.float_value, opb.float_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.float_value = riscv_emulate_fles(opa.float_value, opb.float_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
|
|
|
|
// Sign-injection
|
|
neorv32_uart_printf("FSGNJX.S: ");
|
|
time_sw = 0;
|
|
time_hw = 0;
|
|
err_cnt = 0;
|
|
for (i=0; i<num_runs; i++) {
|
|
opa.binary_value = get_test_vector();
|
|
opb.binary_value = get_test_vector();
|
|
|
|
// hardware execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_hw.float_value = riscv_intrinsic_fsgnjxs(opa.float_value, opb.float_value);
|
|
}
|
|
time_hw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
time_hw -= 4; // remove the 2 dummy instructions
|
|
|
|
// software (emulation) execution time
|
|
time_start = neorv32_cpu_csr_read(CSR_CYCLE);
|
|
{
|
|
res_sw.float_value = riscv_emulate_fsgnjxs(opa.float_value, opb.float_value);
|
|
}
|
|
time_sw += neorv32_cpu_csr_read(CSR_CYCLE) - time_start;
|
|
|
|
if (res_sw.binary_value != res_hw.binary_value) {
|
|
err_cnt++;
|
|
}
|
|
}
|
|
|
|
if (err_cnt == 0) {
|
|
neorv32_uart_printf("cycles[SW] = %u vs. cycles[HW] = %u\n", time_sw/num_runs, time_hw/num_runs);
|
|
}
|
|
else {
|
|
neorv32_uart_printf("%c[1m[TEST FAILED!]%c[0m\n", 27, 27);
|
|
err_cnt_total++;
|
|
}
|
|
#endif
|
|
|
|
|
|
// ----------------------------------------------------------------------------
|
|
// Final report
|
|
// ----------------------------------------------------------------------------
|
|
|
if (err_cnt_total != 0) {
|
if (err_cnt_total != 0) {
|
neorv32_uart_printf("\n%c[1m[ZFINX EXTENSION VERIFICATION FAILED!]%c[0m\n", 27, 27);
|
neorv32_uart_printf("\n%c[1m[ZFINX EXTENSION VERIFICATION FAILED!]%c[0m\n", 27, 27);
|
neorv32_uart_printf("%u errors in %u test cases\n", err_cnt_total, test_cnt*(uint32_t)NUM_TEST_CASES);
|
neorv32_uart_printf("%u errors in %u test cases\n", err_cnt_total, test_cnt*(uint32_t)NUM_TEST_CASES);
|
}
|
}
|
else {
|
else {
|
| Line 527... |
Line 848... |
}
|
}
|
else {
|
else {
|
tmp.binary_value = xorshift32();
|
tmp.binary_value = xorshift32();
|
}
|
}
|
|
|
// subnormal numbers are not supported yet!
|
|
// flush them to zero
|
|
//tmp.float_value = subnormal_flush(tmp.float_value);
|
|
|
|
return tmp.binary_value;
|
return tmp.binary_value;
|
}
|
}
|
|
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
