| Line 81... |
Line 81... |
/**********************************************************************//**
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/**********************************************************************//**
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* High-level CPU/processor test program.
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* High-level CPU/processor test program.
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*
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*
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* @note Applications has to be compiler with <USER_FLAGS+=-DRUN_CPUTEST>
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* @note Applications has to be compiler with <USER_FLAGS+=-DRUN_CPUTEST>
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*
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*
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* @return Irrelevant.
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* @return 0 if execution was successful
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**************************************************************************/
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**************************************************************************/
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int main() {
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int main() {
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register uint32_t tmp_a, tmp_b;
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register uint32_t tmp_a, tmp_b;
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volatile uint32_t dummy_dst __attribute__((unused));
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volatile uint32_t dummy_dst __attribute__((unused));
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| Line 101... |
Line 101... |
#warning processor_check HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.
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#warning processor_check HAS NOT BEEN COMPILED! Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.
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// inform the user if you are actually executing this
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// inform the user if you are actually executing this
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neorv32_uart_printf("ERROR! processor_check has not been compiled. Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.\n");
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neorv32_uart_printf("ERROR! processor_check has not been compiled. Use >>make USER_FLAGS+=-DRUN_CHECK clean_all exe<< to compile it.\n");
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return 0;
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return 1;
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#endif
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#endif
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// check if this is a simulation (using primary UART0)
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// check if this is a simulation (using primary UART0)
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if (UART0_CT & (1 << UART_CT_SIM_MODE)) {
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if (UART0_CT & (1 << UART_CT_SIM_MODE)) {
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is_simulation = 1;
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is_simulation = 1;
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| Line 164... |
Line 164... |
install_err += neorv32_rte_exception_install(id, global_trap_handler);
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install_err += neorv32_rte_exception_install(id, global_trap_handler);
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}
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}
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if (install_err) {
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if (install_err) {
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neorv32_uart_printf("RTE install error (%i)!\n", install_err);
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neorv32_uart_printf("RTE install error (%i)!\n", install_err);
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return 0;
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return 1;
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}
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}
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// enable interrupt sources
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// enable interrupt sources
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neorv32_cpu_irq_enable(CSR_MIE_MSIE); // machine software interrupt
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neorv32_cpu_irq_enable(CSR_MIE_MSIE); // machine software interrupt
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neorv32_cpu_irq_enable(CSR_MIE_MTIE); // machine timer interrupt
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neorv32_cpu_irq_enable(CSR_MIE_MTIE); // machine timer interrupt
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| Line 787... |
Line 787... |
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Machine timer interrupt (MTIME)
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// Machine timer interrupt (MTIME)
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] MTI (machine timer) IRQ: ", cnt_test);
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neorv32_uart_printf("[%i] MTI (via MTIME): ", cnt_test);
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if (neorv32_mtime_available()) {
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if (neorv32_mtime_available()) {
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cnt_test++;
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cnt_test++;
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// configure MTIME IRQ (and check overflow form low owrd to high word)
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// configure MTIME IRQ (and check overflow form low owrd to high word)
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| Line 826... |
Line 826... |
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Machine software interrupt (MSI) via testbench
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// Machine software interrupt (MSI) via testbench
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] MSI (via testbench) IRQ: ", cnt_test);
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neorv32_uart_printf("[%i] MSI (via testbench): ", cnt_test);
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if (is_simulation) { // check if this is a simulation
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if (is_simulation) { // check if this is a simulation
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cnt_test++;
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cnt_test++;
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// trigger IRQ
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// trigger IRQ
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| Line 854... |
Line 854... |
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Machine external interrupt (MEI) via testbench
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// Machine external interrupt (MEI) via testbench
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] MEI (via testbench) IRQ: ", cnt_test);
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neorv32_uart_printf("[%i] MEI (via testbench): ", cnt_test);
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if (is_simulation) { // check if this is a simulation
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if (is_simulation) { // check if this is a simulation
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cnt_test++;
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cnt_test++;
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// trigger IRQ
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// trigger IRQ
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| Line 882... |
Line 882... |
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Non-maskable interrupt (NMI) via testbench
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// Non-maskable interrupt (NMI) via testbench
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_uart_printf("[%i] NMI (via testbench) IRQ: ", cnt_test);
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neorv32_uart_printf("[%i] NMI (via testbench): ", cnt_test);
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if (is_simulation) { // check if this is a simulation
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if (is_simulation) { // check if this is a simulation
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cnt_test++;
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cnt_test++;
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// trigger IRQ
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// trigger IRQ
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| Line 1689... |
Line 1689... |
neorv32_uart_printf("\n\nTest results:\nOK: %i/%i\nFAILED: %i/%i\n\n", cnt_ok, cnt_test, cnt_fail, cnt_test);
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neorv32_uart_printf("\n\nTest results:\nOK: %i/%i\nFAILED: %i/%i\n\n", cnt_ok, cnt_test, cnt_fail, cnt_test);
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// final result
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// final result
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if (cnt_fail == 0) {
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if (cnt_fail == 0) {
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neorv32_uart_printf("%c[1m[CPU TEST COMPLETED SUCCESSFULLY!]%c[0m\n", 27, 27);
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neorv32_uart_printf("%c[1m[CPU TEST COMPLETED SUCCESSFULLY!]%c[0m\n", 27, 27);
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return 0;
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}
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}
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else {
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else {
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neorv32_uart_printf("%c[1m[CPU TEST FAILED!]%c[0m\n", 27, 27);
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neorv32_uart_printf("%c[1m[CPU TEST FAILED!]%c[0m\n", 27, 27);
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return 1;
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}
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}
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return 0;
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}
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}
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/**********************************************************************//**
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/**********************************************************************//**
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* Simulation-based function to trigger CPU interrupts (MSI, MEI, FIRQ4..7).
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* Simulation-based function to trigger CPU interrupts (MSI, MEI, FIRQ4..7).
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