| Line 199... |
Line 199... |
neorv32_cpu_csr_write(CSR_MIE, 0);
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neorv32_cpu_csr_write(CSR_MIE, 0);
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// test intro
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// test intro
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PRINT_STANDARD("\nStarting tests.\n\n");
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PRINT_STANDARD("\nStarting tests.\n\n");
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// sync (test)
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asm volatile ("fence.i");
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// enable global interrupts
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// enable global interrupts
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neorv32_cpu_eint();
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neorv32_cpu_eint();
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// **********************************************************************************************
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// **********************************************************************************************
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| Line 443... |
Line 446... |
PRINT_STANDARD("skipped (n.a.)\n");
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PRINT_STANDARD("skipped (n.a.)\n");
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}
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}
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Test FENCE.I instruction (instruction buffer / i-cache clear & reload)
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// if Zifencei is not implemented FENCE.I should execute as NOP
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] FENCE.I: ", cnt_test);
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cnt_test++;
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asm volatile ("fence.i");
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// make sure there was no exception (and that the cpu did not crash...)
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == 0) {
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test_ok();
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}
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else {
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test_fail();
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}
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// ----------------------------------------------------------
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// Illegal CSR access (CSR not implemented)
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// Illegal CSR access (CSR not implemented)
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] Non-existent CSR access: ", cnt_test);
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PRINT_STANDARD("[%i] Non-existent CSR access: ", cnt_test);
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| Line 1309... |
Line 1292... |
// shutdown SLINK
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// shutdown SLINK
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neorv32_slink_disable();
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neorv32_slink_disable();
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}
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}
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// ----------------------------------------------------------
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// Fast interrupt channel 12 (GPTMR)
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// ----------------------------------------------------------
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if (neorv32_slink_available()) {
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neorv32_cpu_csr_write(CSR_MCAUSE, 0);
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PRINT_STANDARD("[%i] FIRQ12 (GPTMR): ", cnt_test);
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|
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cnt_test++;
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|
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// enable GPTMR FIRQ
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neorv32_cpu_irq_enable(CSR_MIE_FIRQ12E);
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|
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// configure timer IRQ for one-shot mode after 2*4 clock cycles
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neorv32_gptmr_setup(CLK_PRSC_2, 0, 4);
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// wait some time for the IRQ to arrive the CPU
|
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asm volatile("nop");
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asm volatile("nop");
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// disable GPTMR interrupt
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neorv32_cpu_irq_disable(CSR_MIE_FIRQ12E);
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|
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// check if RX FIFO fires IRQ
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if (neorv32_cpu_csr_read(CSR_MCAUSE) == TRAP_CODE_FIRQ_12) {
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test_ok();
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}
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else {
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test_fail();
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}
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|
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// disable GPTMR
|
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neorv32_gptmr_disable();
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}
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//// ----------------------------------------------------------
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//// ----------------------------------------------------------
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//// Fast interrupt channel 12..15 (reserved)
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//// Fast interrupt channel 13..15 (reserved)
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//// ----------------------------------------------------------
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//// ----------------------------------------------------------
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//PRINT_STANDARD("[%i] FIRQ12..15: ", cnt_test);
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//PRINT_STANDARD("[%i] FIRQ13..15: ", cnt_test);
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//PRINT_STANDARD("skipped (n.a.)\n");
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//PRINT_STANDARD("skipped (n.a.)\n");
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|
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// ----------------------------------------------------------
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// ----------------------------------------------------------
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// Test WFI ("sleep") instructions, wakeup via MTIME
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// Test WFI ("sleep") instructions, wakeup via MTIME
|
