| Line 69... |
Line 69... |
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
|
CSR_MEPC = 0x341, /**< 0x341 - mepc (r/w): Machine exception program counter */
|
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/-): Machine trap cause */
|
CSR_MCAUSE = 0x342, /**< 0x342 - mcause (r/-): Machine trap cause */
|
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */
|
CSR_MTVAL = 0x343, /**< 0x343 - mtval (r/-): Machine bad address or instruction */
|
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
|
CSR_MIP = 0x344, /**< 0x344 - mip (r/w): Machine interrupt pending register */
|
|
|
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/-): Machine cycle counter low word */
|
CSR_MCYCLE = 0xb00, /**< 0xb00 - mcycle (r/w): Machine cycle counter low word */
|
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/-): Machine instructions-retired counter low word */
|
CSR_MINSTRET = 0xb02, /**< 0xb02 - minstret (r/w): Machine instructions-retired counter low word */
|
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/-): Machine cycle counter high word */
|
CSR_MCYCLEH = 0xb80, /**< 0xb80 - mcycleh (r/w): Machine cycle counter high word */
|
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/-): Machine instructions-retired counter high word */
|
CSR_MINSTRETH = 0xb82, /**< 0xb82 - minstreth (r/w): Machine instructions-retired counter high word */
|
|
|
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word */
|
CSR_CYCLE = 0xc00, /**< 0xc00 - cycle (r/-): Cycle counter low word */
|
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word*/
|
CSR_TIME = 0xc01, /**< 0xc01 - time (r/-): Timer low word (from MTIME.TIME) */
|
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word */
|
CSR_INSTRET = 0xc02, /**< 0xc02 - instret (r/-): Instructions-retired counter low word */
|
|
|
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word */
|
CSR_CYCLEH = 0xc80, /**< 0xc80 - cycleh (r/-): Cycle counter high word */
|
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word*/
|
CSR_TIMEH = 0xc81, /**< 0xc81 - timeh (r/-): Timer high word (from MTIME.TIME) */
|
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */
|
CSR_INSTRETH = 0xc82, /**< 0xc82 - instreth (r/-): Instructions-retired counter high word */
|
|
|
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
|
CSR_MIMPID = 0xf13, /**< 0xf13 - mimpid (r/-): Implementation ID/version */
|
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (via HART_ID generic) */
|
CSR_MHARTID = 0xf14, /**< 0xf14 - mhartid (r/-): Hardware thread ID (via HART_ID generic) */
|
|
|
| Line 127... |
Line 127... |
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.)
|
* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.)
|
**************************************************************************/
|
**************************************************************************/
|
enum NEORV32_CPU_MISA_enum {
|
enum NEORV32_CPU_MISA_enum {
|
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/w), can be switched on/off */
|
CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-), can be switched on/off */
|
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
|
CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
|
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
|
CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
|
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/w), can be switched on/off */
|
CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-), can be switched on/off */
|
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
|
CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
|
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */
|
CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */
|
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
|
CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
|
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
|
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
|
};
|
};
|
| Line 322... |
Line 322... |
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* @name IO Device: Machine System Timer (MTIME)
|
* @name IO Device: Machine System Timer (MTIME)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** MTIME (time register) low word (r/-) */
|
/** MTIME (time register) low word (r/w) */
|
#define MTIME_LO (*(IO_ROM32 0xFFFFFF90UL))
|
#define MTIME_LO (*(IO_REG32 0xFFFFFF90UL))
|
/** MTIME (time register) high word (r/-) */
|
/** MTIME (time register) high word (r/w) */
|
#define MTIME_HI (*(IO_ROM32 0xFFFFFF94UL))
|
#define MTIME_HI (*(IO_REG32 0xFFFFFF94UL))
|
/** MTIMECMP (time compare register) low word (r/w) */
|
/** MTIMECMP (time compare register) low word (r/w) */
|
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL))
|
#define MTIMECMP_LO (*(IO_REG32 0xFFFFFF98UL))
|
/** MTIMECMP (time register) high word (r/w) */
|
/** MTIMECMP (time register) high word (r/w) */
|
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL))
|
#define MTIMECMP_HI (*(IO_REG32 0xFFFFFF9CUL))
|
|
|
/** MTIME (time register) 64-bit access (r/-) */
|
/** MTIME (time register) 64-bit access (r/w) */
|
#define MTIME (*(IO_ROM64 (&MTIME_LO)))
|
#define MTIME (*(IO_REG64 (&MTIME_LO)))
|
/** MTIMECMP (time compare register) low word (r/w) */
|
/** MTIMECMP (time compare register) low word (r/w) */
|
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO)))
|
#define MTIMECMP (*(IO_REG64 (&MTIMECMP_LO)))
|
/**@}*/
|
/**@}*/
|
|
|
|
|
