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/**********************************************************************//**
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/**********************************************************************//**
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* @file neorv32.h
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* @file neorv32.h
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* @author Stephan Nolting
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* @author Stephan Nolting
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* @date 30 May 2020
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*
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*
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* @brief Main NEORV32 core library file.
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* @brief Main NEORV32 core library file.
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*
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*
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* @details This file defines the addresses of the IO devices and their according
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* @details This file defines the addresses of the IO devices and their according
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* registers and register bits as well as the available CPU CSRs and flags.
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* registers and register bits as well as the available CPU CSRs and flags.
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CPU_MIP_FIRQ3P = 19 /**< CPU mip CSR (19): Fast interrupt channel 3 pending (r/-) */
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CPU_MIP_FIRQ3P = 19 /**< CPU mip CSR (19): Fast interrupt channel 3 pending (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>misa</b> CSR (r/w): Machine instruction set extensions (RISC-V spec.)
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* CPU <b>misa</b> CSR (r/-): Machine instruction set extensions (RISC-V spec.)
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_CPU_MISA_enum {
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enum NEORV32_CPU_MISA_enum {
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CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
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CPU_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
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CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
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CPU_MISA_E_EXT = 4, /**< CPU misa CSR (3): E: Embedded CPU extension available (r/-) */
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CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
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CPU_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
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CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
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CPU_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
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CPU_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
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CPU_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
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CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
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CPU_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
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CPU_MISA_Z_EXT = 25, /**< CPU misa CSR (25): Z: Privileged architecture CPU extension(s) available (r/-) */
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CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
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CPU_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
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CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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};
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};
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