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| Rev 32 |
Rev 33 |
| Line 153... |
Line 153... |
CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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CPU_MISA_MXL_HI_EXT = 31 /**< CPU misa CSR (31): MXL.Hi: CPU data width (r/-) */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* CPU <b>mzext</b> custom CSR (r/-): Implemented Z* CPU extensions
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**************************************************************************/
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enum NEORV32_CPU_MZEXT_enum {
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CPU_MZEXT_ZICSR = 0, /**< CPU mzext CSR (0): Zicsr extension available when set (r/-) */
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CPU_MZEXT_ZIFENCEI = 1, /**< CPU mzext CSR (1): Zifencei extension available when set (r/-) */
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CPU_MZEXT_PMP = 2 /**< CPU mzext CSR (2): PMP extension available when set (r/-) */
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};
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/**********************************************************************//**
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* Trap codes from mcause CSR.
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* Trap codes from mcause CSR.
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_EXCEPTION_CODES_enum {
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enum NEORV32_EXCEPTION_CODES_enum {
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TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
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TRAP_CODE_I_MISALIGNED = 0x00000000, /**< 0.0: Instruction address misaligned */
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TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */
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TRAP_CODE_I_ACCESS = 0x00000001, /**< 0.1: Instruction (bus) access fault */
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