URL
https://opencores.org/ocsvn/neorv32/neorv32/trunk
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 34 |
Rev 35 |
| Line 421... |
Line 421... |
TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
|
TWI_CT_IRQ_EN = 3, /**< TWI control register(3) (r/w): Enable transmission done interrupt */
|
TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
|
TWI_CT_PRSC0 = 4, /**< TWI control register(4) (r/w): Clock prescaler select bit 0 */
|
TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
|
TWI_CT_PRSC1 = 5, /**< TWI control register(5) (r/w): Clock prescaler select bit 1 */
|
TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
|
TWI_CT_PRSC2 = 6, /**< TWI control register(6) (r/w): Clock prescaler select bit 2 */
|
TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
|
TWI_CT_MACK = 7, /**< TWI control register(7) (r/w): Generate controller ACK for each transmission */
|
|
TWI_CT_CKSTEN = 8, /**< TWI control register(8) (r/w): Enable clock stretching (by peripheral) */
|
|
|
TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
|
TWI_CT_ACK = 30, /**< TWI control register(30) (r/-): ACK received when set */
|
TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
|
TWI_CT_BUSY = 31 /**< TWI control register(31) (r/-): Transfer in progress, busy flag */
|
};
|
};
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.