| Line 422... |
Line 422... |
**************************************************************************/
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**************************************************************************/
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enum NEORV32_CSR_MISA_enum {
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enum NEORV32_CSR_MISA_enum {
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CSR_MISA_A_EXT = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/
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CSR_MISA_A_EXT = 0, /**< CPU misa CSR (0): A: Atomic instructions CPU extension available (r/-)*/
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CSR_MISA_B_EXT = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/
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CSR_MISA_B_EXT = 1, /**< CPU misa CSR (1): B: Bit manipulation CPU extension available (r/-)*/
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CSR_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
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CSR_MISA_C_EXT = 2, /**< CPU misa CSR (2): C: Compressed instructions CPU extension available (r/-)*/
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CSR_MISA_D_EXT = 3, /**< CPU misa CSR (3): D: Double-precision floating-point extension available (r/-)*/
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CSR_MISA_E_EXT = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */
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CSR_MISA_E_EXT = 4, /**< CPU misa CSR (4): E: Embedded CPU extension available (r/-) */
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CSR_MISA_F_EXT = 5, /**< CPU misa CSR (5): F: Single-precision floating-point extension available (r/-)*/
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CSR_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
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CSR_MISA_I_EXT = 8, /**< CPU misa CSR (8): I: Base integer ISA CPU extension available (r/-) */
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CSR_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
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CSR_MISA_M_EXT = 12, /**< CPU misa CSR (12): M: Multiplier/divider CPU extension available (r/-)*/
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CSR_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
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CSR_MISA_U_EXT = 20, /**< CPU misa CSR (20): U: User mode CPU extension available (r/-)*/
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CSR_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
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CSR_MISA_X_EXT = 23, /**< CPU misa CSR (23): X: Non-standard CPU extension available (r/-) */
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CSR_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
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CSR_MISA_MXL_LO_EXT = 30, /**< CPU misa CSR (30): MXL.lo: CPU data width (r/-) */
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| Line 505... |
Line 507... |
TRAP_CODE_FIRQ_15 = 0x8000001f /**< 1.31: Fast interrupt channel 15 */
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TRAP_CODE_FIRQ_15 = 0x8000001f /**< 1.31: Fast interrupt channel 15 */
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};
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};
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/**********************************************************************//**
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/**********************************************************************//**
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* Processor clock prescalers
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* Processor clock prescalers select
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**************************************************************************/
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**************************************************************************/
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enum NEORV32_CLOCK_PRSC_enum {
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enum NEORV32_CLOCK_PRSC_enum {
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CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */
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CLK_PRSC_2 = 0, /**< CPU_CLK (from clk_i top signal) / 2 */
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CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */
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CLK_PRSC_4 = 1, /**< CPU_CLK (from clk_i top signal) / 4 */
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CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */
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CLK_PRSC_8 = 2, /**< CPU_CLK (from clk_i top signal) / 8 */
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| Line 929... |
Line 931... |
#define NCO_CHX_WIDTH 10 // Size of one "channel entry" in control register in bits
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#define NCO_CHX_WIDTH 10 // Size of one "channel entry" in control register in bits
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/**@}*/
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/**@}*/
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/**********************************************************************//**
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/**********************************************************************//**
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* @name IO Device: Smart LED Hardware Interface (NEOLED)
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**************************************************************************/
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/**@{*/
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/** NEOLED control register (r/w) */
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#define NEOLED_CT (*(IO_REG32 0xFFFFFFD8UL)) // r/w: control register
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/** NEOLED TX data register (-/w) */
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#define NEOLED_DATA (*(IO_REG32 0xFFFFFFDCUL)) // -/w: TX data register
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/** NEOLED control register bits */
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enum NEORV32_NEOLED_CT_enum {
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NEOLED_CT_EN = 0, /**< NEOLED control register(0) (r/w): NEOLED global enable */
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NEOLED_CT_MODE = 1, /**< NEOLED control register(1) (r/w): TX mode (0=24-bit, 1=32-bit) */
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NEOLED_CT_BSCON = 2, /**< NEOLED control register(2) (r/w): buffer status configuration -> busy_flag/IRQ config (0=at least one free entry, 1=whole buffer empty) */
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NEOLED_CT_PRSC0 = 3, /**< NEOLED control register(3) (r/w): Clock prescaler select bit 0 (pulse-clock speed select) */
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NEOLED_CT_PRSC1 = 4, /**< NEOLED control register(4) (r/w): Clock prescaler select bit 1 (pulse-clock speed select) */
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NEOLED_CT_PRSC2 = 5, /**< NEOLED control register(5) (r/w): Clock prescaler select bit 2 (pulse-clock speed select) */
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//
|
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NEOLED_CT_BUFS_0 = 6, /**< NEOLED control register(6) (r/-): log2(tx buffer size) bit 0 */
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NEOLED_CT_BUFS_1 = 7, /**< NEOLED control register(7) (r/-): log2(tx buffer size) bit 1 */
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NEOLED_CT_BUFS_2 = 8, /**< NEOLED control register(8) (r/-): log2(tx buffer size) bit 2 */
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NEOLED_CT_BUFS_3 = 9, /**< NEOLED control register(9) (r/-): log2(tx buffer size) bit 3 */
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|
//
|
|
NEOLED_CT_T_TOT_0 = 10, /**< NEOLED control register(10) (r/w): pulse-clock ticks per total period bit 0 */
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NEOLED_CT_T_TOT_1 = 11, /**< NEOLED control register(11) (r/w): pulse-clock ticks per total period bit 1 */
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NEOLED_CT_T_TOT_2 = 12, /**< NEOLED control register(12) (r/w): pulse-clock ticks per total period bit 2 */
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NEOLED_CT_T_TOT_3 = 13, /**< NEOLED control register(13) (r/w): pulse-clock ticks per total period bit 3 */
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NEOLED_CT_T_TOT_4 = 14, /**< NEOLED control register(14) (r/w): pulse-clock ticks per total period bit 4 */
|
|
//
|
|
NEOLED_CT_T_ZERO_H_0 = 15, /**< NEOLED control register(15) (r/w): pulse-clock ticks per ZERO high-time bit 0 */
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NEOLED_CT_T_ZERO_H_1 = 16, /**< NEOLED control register(16) (r/w): pulse-clock ticks per ZERO high-time bit 1 */
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NEOLED_CT_T_ZERO_H_2 = 17, /**< NEOLED control register(17) (r/w): pulse-clock ticks per ZERO high-time bit 2 */
|
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NEOLED_CT_T_ZERO_H_3 = 18, /**< NEOLED control register(18) (r/w): pulse-clock ticks per ZERO high-time bit 3 */
|
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NEOLED_CT_T_ZERO_H_4 = 19, /**< NEOLED control register(19) (r/w): pulse-clock ticks per ZERO high-time bit 4 */
|
|
//
|
|
NEOLED_CT_T_ONE_H_0 = 20, /**< NEOLED control register(20) (r/w): pulse-clock ticks per ONE high-time bit 0 */
|
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NEOLED_CT_T_ONE_H_1 = 21, /**< NEOLED control register(21) (r/w): pulse-clock ticks per ONE high-time bit 1 */
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NEOLED_CT_T_ONE_H_2 = 22, /**< NEOLED control register(22) (r/w): pulse-clock ticks per ONE high-time bit 2 */
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NEOLED_CT_T_ONE_H_3 = 23, /**< NEOLED control register(23) (r/w): pulse-clock ticks per ONE high-time bit 3 */
|
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NEOLED_CT_T_ONE_H_4 = 24, /**< NEOLED control register(24) (r/w): pulse-clock ticks per ONE high-time bit 4 */
|
|
//
|
|
NEOLED_CT_TX_STATUS = 30, /**< NEOLED control register(30) (r/-): serial transmit engine still busy when set */
|
|
NEOLED_CT_BUSY = 31 /**< NEOLED control register(31) (r/-): busy / buffer status flag (configured via #NEOLED_CT_BSCON) */
|
|
};
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/**@}*/
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|
|
|
|
|
/**********************************************************************//**
|
* @name IO Device: System Configuration Info Memory (SYSINFO)
|
* @name IO Device: System Configuration Info Memory (SYSINFO)
|
**************************************************************************/
|
**************************************************************************/
|
/**@{*/
|
/**@{*/
|
/** SYSINFO(0): Clock speed */
|
/** SYSINFO(0): Clock speed */
|
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
|
#define SYSINFO_CLK (*(IO_ROM32 0xFFFFFFE0UL))
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| Line 972... |
Line 1021... |
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
|
SYSINFO_FEATURES_IO_PWM = 21, /**< SYSINFO_FEATURES (21) (r/-): Pulse-width modulation unit implemented when 1 (via IO_PWM_EN generic) */
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SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
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SYSINFO_FEATURES_IO_WDT = 22, /**< SYSINFO_FEATURES (22) (r/-): Watchdog timer implemented when 1 (via IO_WDT_EN generic) */
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SYSINFO_FEATURES_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
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SYSINFO_FEATURES_IO_CFS = 23, /**< SYSINFO_FEATURES (23) (r/-): Custom functions subsystem implemented when 1 (via IO_CFS_EN generic) */
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SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
|
SYSINFO_FEATURES_IO_TRNG = 24, /**< SYSINFO_FEATURES (24) (r/-): True random number generator implemented when 1 (via IO_TRNG_EN generic) */
|
SYSINFO_FEATURES_IO_NCO = 25, /**< SYSINFO_FEATURES (25) (r/-): Numerically-controlled oscillator implemented when 1 (via IO_NCO_EN generic) */
|
SYSINFO_FEATURES_IO_NCO = 25, /**< SYSINFO_FEATURES (25) (r/-): Numerically-controlled oscillator implemented when 1 (via IO_NCO_EN generic) */
|
SYSINFO_FEATURES_IO_UART1 = 26 /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
|
SYSINFO_FEATURES_IO_UART1 = 26, /**< SYSINFO_FEATURES (26) (r/-): Secondary universal asynchronous receiver/transmitter 1 implemented when 1 (via IO_UART1_EN generic) */
|
|
SYSINFO_FEATURES_IO_NEOLED = 27 /**< SYSINFO_FEATURES (27) (r/-): NeoPixel-compatible smart LED interface implemented when 1 (via IO_NEOLED_EN generic) */
|
};
|
};
|
|
|
/**********************************************************************//**
|
/**********************************************************************//**
|
* SYSINFO_CACHE (r/-): Cache configuration
|
* SYSINFO_CACHE (r/-): Cache configuration
|
**************************************************************************/
|
**************************************************************************/
|
| Line 1015... |
Line 1065... |
// io/peripheral devices
|
// io/peripheral devices
|
#include "neorv32_cfs.h"
|
#include "neorv32_cfs.h"
|
#include "neorv32_gpio.h"
|
#include "neorv32_gpio.h"
|
#include "neorv32_mtime.h"
|
#include "neorv32_mtime.h"
|
#include "neorv32_nco.h"
|
#include "neorv32_nco.h"
|
|
#include "neorv32_neoled.h"
|
#include "neorv32_pwm.h"
|
#include "neorv32_pwm.h"
|
#include "neorv32_spi.h"
|
#include "neorv32_spi.h"
|
#include "neorv32_trng.h"
|
#include "neorv32_trng.h"
|
#include "neorv32_twi.h"
|
#include "neorv32_twi.h"
|
#include "neorv32_uart.h"
|
#include "neorv32_uart.h"
|
